Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

Datasheet

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The MCH supports 64 GB (36 bit) of host address space and 64 KB+3 of addressable 

I/O space. There is a programmable memory address space under the 1 MB region 

which is divided into regions which can be individually controlled with programmable 

attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute 

programming is described in the Register Description section. This section focuses on 

how the memory space is partitioned and what the separate memory regions are used 

for. I/O address space has simpler mapping and is explained near the end of this 

section.

The MCH supports PCI Express* upper pre-fetchable base/limit registers. This allows 

the PCI Express unit to claim IO accesses above 36 bit, complying with the PCI Express 

Specification. Addressing of greater than 8 GB is allowed on either the DMI Interface or 

PCI Express interface. The MCH supports a maximum of 8 GB of DRAM. No DRAM 

memory will be accessible above 8 GB.

In the following sections, it is assumed that all of the compatibility memory ranges 

reside on the DMI Interface. The MCH does not remap APIC or any other memory 

spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the 

appropriate value by BIOS. The reclaim base/reclaim limit registers remap logical 

accesses bound for addresses above 4 GB onto physical addresses that fall within 

DRAM.

The Address Map includes a number of programmable ranges:

• Device 0

— PXPEPBAR – Egress port registers. Necessary for setting up VC1 as an 

isochronous channel using time based weighted round robin arbitration. (4 KB 

window)

— MCHBAR – Memory mapped range for internal MCH registers. For example, 

memory buffer register controls. (16 KB window)

— PCIEXBAR – Flat memory-mapped address spaced to access device 

configuration registers. This mechanism can be used to access PCI 

configuration space (0–FFh) and Extended configuration space (100h–FFFh) for 

PCI Express devices. This enhanced configuration access mechanism is defined 

in the PCI Express specification. (64 MB, 128 MB, or 256 MB window).

— DMIBAR –This window is used to access registers associated with the Direct 

Media Interface (DMI) register memory range. (4 KB window)

• Device 1

— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window. 
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access 

window

— IOBASE1/IOLIMIT1 – PCI Express port I/O access window.