Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

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Datasheet

This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can be 

assigned read and write attributes. It is by default (after reset) Read/Write disabled 

and cycles are forwarded to DMI Interface. By manipulating the Read/Write attributes, 

the MCH can “shadow” BIOS into the main DRAM. When disabled, this segment is not 

remapped.

Non-snooped accesses from PCI Express or DMI to this region are always sent to 

DRAM. 

The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory 

Area.

The MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all 

memory residing on DMI should be set as non-cacheable, there will normally not be 

IWB cycles targeting DMI. However, DMI becomes the default target for processor and 

DMI originated accesses to disabled segments of the PAM region. If the MTRRs covering 

the PAM regions are set to WB or RD it is possible to get IWB cycles targeting DMI. This 

may occur for processor originated cycles (in a DP system) and for DMI originated 

cycles to disabled PAM regions.

For example, say that a particular PAM region is set for “Read Disabled” and the MTRR 

associated with this region is set to WB. A DMI master generates a memory read 

targeting the PAM region. A snoop is generated on the FSB and the result is an IWB. 

Since the PAM region is “Read Disabled” the default target for the Memory Read 

becomes DMI. The IWB associated with this cycle will cause the MCH to hang.

Non-snooped accesses from PCI Express or DMI to this region are always sent to 

DRAM. 

This address range extends from 1 MB to the top of Low Usable physical memory that is 

permitted to be accessible by the MCH (as programmed in the TOLUD register). All 

accesses to addresses within this range will be forwarded by the MCH to the DRAM 

unless it falls into the optional TSEG, or optional ISA Hole. 

0F0000h – 0FFFFFh

WE   RE

BIOS Area