Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

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Datasheet

As with PCI devices, each device is selected based on decoded address information that 
is provided as a part of the address portion of Configuration Request packets. A PCI 
Express device will decode all address information fields (bus, device, function and 
extended address numbers) to provide access to the correct register. 

To access this space (steps 1, 2, 3 are done only once by BIOS), 

1. Use the PCI compatible configuration mechanism to enable the PCI Express 

enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register.

2. Use the PCI compatible configuration mechanism to write an appropriate PCI 

Express base address into the PCIEXBAR register.

3. Calculate the host address of the register you wish to set using (PCI Express base 

+ (bus number * 1 MB) + (device number * 32KB) + (function number * 4 KB) + 
(1 B * offset within the function) = host address).

4. Use a memory write or memory read cycle to the calculated host address to write 

or read that register.

The MCH supports two PCI related interfaces: DMI and PCI Express. The MCH is 
responsible for routing PCI and PCI Express configuration cycles to the appropriate 
device that is an integrated part of the MCH or to one of these two interfaces. 
Configuration cycles to the ICH internal devices and Primary PCI (including downstream 
devices) are routed to the ICH via DMI. Configuration cycles to the PCI Express PCI 
compatibility configuration space are routed to the PCI Express port device or 
associated link. 

MemMap PCIExpress

Bus 255

FFFFFFFh

Bus 1

Bus 0

1FFFFFh

FFFFFh

0h

Device 31

FFFFFh

Device 1

Device 0

FFFFh

7FFFh

Function 7

7FFFh

Function 1

Function 0

1FFFh

FFFh

FFFh

PCI 

Compatible 

Config Space

PCI 

Compatible 

Config Header

FFh

3Fh

PCI Express* 

Extended 

Configuration 

Space

Located By PCI 

Express* Base 

Address