Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

Datasheet

65

The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).

Address locations that are not listed are considered Intel Reserved registers locations. 

Reads to Reserved registers may return non-zero values. Writes to reserved locations 

may cause system failures.

All registers that are defined in the PCI 2.3 specification, but are not necessary or 

implemented in this component are simply not included in this document. The 

reserved/unimplemented space in the PCI configuration header space is not 

documented as such in this summary.

0–1h

VID

Vendor Identification

8086h

RO

2–3h

DID

Device Identification

29F0h

RO

4–5h

PCICMD

PCI Command

0006h

RO, RW 

6–7h

PCISTS

PCI Status

0090h

RO, RWC

8h

RID

Revision Identification

see register 

description

RO

9–Bh

CC

Class Code

060000h

RO

Dh

MLT

Master Latency Timer

00h

RO

Eh

HDR

Header Type

00h

RO

2C–2Dh

SVID

Subsystem Vendor Identification

0000h

RWO

2E–2Fh

SID

Subsystem Identification

0000h

RWO

34h

CAPPTR

Capabilities Pointer

E0h

RO

40–47h

PXPEPBAR

PCI Express Egress Port Base Address

0000000000

000000h

RO, RW/L

48–4Fh

MCHBAR

MCH Memory Mapped Register Range 
Base

0000000000

000000h

RO, RW/L

54–57h

DEVEN

Device Enable

000023DBh

RO, RW/L

60–67h

PCIEXBAR

PCI Express Register Range Base 
Address

00000000E0

000000h

RO, RW/L, 

RW/L/K

68–6Fh

DMIBAR

Root Complex Register Range Base 
Address

0000000000

000000h

RO, RW/L

90h

PAM0

Programmable Attribute Map 0

00h

RO, RW/L

91h

PAM1

Programmable Attribute Map 1

00h

RO, RW/L

92h

PAM2

Programmable Attribute Map 2

00h

RO, RW/L 

93h

PAM3

Programmable Attribute Map 3

00h

RO, RW/L

94h

PAM4

Programmable Attribute Map 4

00h

RO, RW/L