Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

Datasheet

75

B/D/F/Type:

0/0/0/PCI

Address Offset: 60–67h

Default Value:

00000000E0000000h

Access:

RO, RW/L, RW/L/K 

Size:

64 bits

This is the base address for the PCI Express configuration space. This window of 

addresses contains the 4 KB of configuration space for each PCI Express device that 

can potentially be part of the PCI Express Hierarchy associated with the MCH. There is 

not actual physical memory within this window of up to 256 MB that can be addressed. 

The actual length is determined by a field in this register. Each PCI Express Hierarchy 

requires a PCI Express BASE register. The MCH supports one PCI Express hierarchy. 

The region reserved by this register does not alias to any PCI 2.3 compliant memory 

mapped space. 

On reset, this register is disabled and must be enabled by writing a 1 to the enable field 

in this register. This base address shall be assigned on a boundary consistent with the 

number of buses (defined by the Length field in this register), above TOLUD and still 

within 64 bit addressable memory space. All other bits not decoded are read only 0. 

The PCI Express Base Address cannot be less than the maximum address written to the 

Top of physical memory register (TOLUD). Software must guarantee that these ranges 

do not overlap with known ranges located above TOLUD. Software must ensure that the 

sum of Length of enhanced configuration region + TOLUD + (other known ranges 

reserved above TOLUD) is not greater than the 64-bit addressable limit of 64 GB. In 

general system implementation and number of PCI/PCI express/PCI-X buses supported 

in the hierarchy will dictate the length of the region.

All the Bits in this register are locked in Intel TXT mode.

5:2

RO

0s

Reserved

1

RW/L

1b

PCI Express Port (D1EN): 
0 = Bus 0, Device 1, Function 0 is disabled and hidden. 
Bus 0, Device 1, Function 0 is enabled and visible. 

0

RO

1b

Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be disabled and is 
therefore hardwired to 1.