Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
78
Datasheet
5.1.17
PAM0—Programmable Attribute Map 0
B/D/F/Type:
0/0/0/PCI
Address Offset: 90h
Default Value:
00h
Access:
RO, RW/L
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h–0FFFFFh. The MCH allows programmable memory attributes on 13 Legacy
memory segments of various sizes in the 768 KB to 1 MB address range. Seven
Programmable Attribute Map (PAM) Registers are used to support these features.
Cacheability of these areas is controlled via the MTRR registers in the processor. Two
bits are used to specify memory attributes for each memory segment. These bits apply
to both host accesses and PCI initiator accesses to the PAM areas. These attributes are:
RE - Read Enable.
When RE = 1, the processor read accesses to the
corresponding memory segment are claimed by the MCH and
directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to PCI_A.
WE - Write Enable.
When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main
memory. Conversely, when WE = 0, the host write accesses are
directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in
size.
Note that the MCH may hang if a PCI Express Link Attach or DMI originated access to
Read Disabled or Write Disabled PAM segments occur (due to a possible IWB to non-
DRAM).
For these reasons the following critical restriction is placed on the programming of the
PAM regions: At the time that a DMI or PCI Express Link Attach accesses to the PAM
region may occur, the targeted PAM segment must be programmed to be both readable
and writeable.
Bit
Access
Default
Value
Description
7:6
RO
00b
Reserved
5:4
RW/L
00b
0F0000–0FFFFF Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0F0000h to 0FFFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
read and write cycles that address the BIOS area from 0F0000h to 0FFFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
3:0
RO
0h
Reserved