Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
Datasheet
221
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
8.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
0/6/0/PCI
Address Offset: 19h
Default Value:
00h
Access:
RW
Size:
8 bits
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge. This number is programmed by the PCI configuration software to allow mapping
of configuration cycles to PCI Express.
8.11
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
0/6/0/PCI
Address Offset: 1Ah
Default Value:
00h
Access:
RW
Size:
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express.
Bit
Access
Default
Value
Description
7:0
RW
00h
Secondary Bus Number (BUSN): This field is programmed by configuration
software with the bus number assigned to PCI Express.
software with the bus number assigned to PCI Express.
Bit
Access
Default
Value
Description
7:0
RW
00h
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device #6 bridge. When only a single PCI device resides on the PCI
Express segment, this register will contain the same value as the SBUSN1
register.
configuration software with the number of the highest subordinate bus that lies
behind the device #6 bridge. When only a single PCI device resides on the PCI
Express segment, this register will contain the same value as the SBUSN1
register.