Renesas R5S72643 Manual Do Utilizador
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 541 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
TGRC_3
TDDR
TCNT_3
TGRD_3
TGRD_4
TGRC_4
TGRB_3
Temp 1
TGRA_4
Temp 2
TGRB_4
Temp 3
TCNTS
TCNT_4
TGRA_3
TCDR
TCBR
Comparator
Comparator
Match
signal
Match
signal
: Registers that can always be read or written from the CPU
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
(except for TCNTS, which can only be read)
: Registers that can be read or written from the CPU
(but for which access disabling can be set by TRWER)
(but for which access disabling can be set by TRWER)
TGRA_3 compare-
match interrupt
TCNT_4 underflow
interrupt
PWM cycle
output
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
Output controller
Figure 11.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode