Intel Pentium III BX80525U450512E Ficha De Dados
Códigos do produto
BX80525U450512E
38
Datasheet
Electrical Specifications
Figure 8. System Bus Valid Delay Timings
Figure 9. System Bus Setup and Hold Timings
Figure 10. System Bus Reset and Configuration Timings
CLK
Signal
762
Valid
Valid
Tx
V
Tx
Tpw
Tx = T7, T29, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh)
for APIC and TAP signal groups
Tpw = T14, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh)
for APIC and TAP signal groups
CLK
Signal
Valid
Ts
V
Th
Ts = T8, T27 (Setup Time)
Th = T9, T28 (Hold Time)
V = 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or
0.75V (CPUID 068xh) for APIC and TAP signal groups
Th = T9, T28 (Hold Time)
V = 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or
0.75V (CPUID 068xh) for APIC and TAP signal groups
Valid
T
v
T
w
T
x
T
u
T
t
BCLK
RESET#
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T
t
= T9 (AGTL+ Input Hold Time)
T
u
= T8 (AGTL+ Input Setup Time)
T
v
= T10 (RESET# Pulse Width)
T
w
= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T
x
= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)