Intel Pentium III BX80525U550512E Ficha De Dados
Códigos do produto
BX80525U550512E
98
Datasheet
Intel
®
Pentium
®
III Processor Signal Description
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a Power-on or
“warm” reset, RESET# must stay active for at least one millisecond after Vcc
their L1 and L2 caches without writing back any of their contents. For a Power-on or
“warm” reset, RESET# must stay active for at least one millisecond after Vcc
CORE
and CLK have reached their proper specifications. On observing active RESET#,
all processor system bus agents will deassert their outputs within two clocks.
all processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the P6
Family of Processors Hardware Developer’s Manual (Document Number 244001)
for details.
for power-on configuration. These configuration options are described in the P6
Family of Processors Hardware Developer’s Manual (Document Number 244001)
for details.
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the power on Reset vector
(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all
processor system bus agents.
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the power on Reset vector
(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all
processor system bus agents.
RP#
I/O
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RSP#
I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
SLOTOCC#
O
The SLOTOCC# signal is defined to allow a system design to detect the presence
of a terminator card or processor in a SC242 connector. Combined with the VID
combination of VID[4:0]= 11111 (see
of a terminator card or processor in a SC242 connector. Combined with the VID
combination of VID[4:0]= 11111 (see
), a system can determine if a
SC242 connector is occupied, and whether a processor core is present. See the
table below for states and values for determining the type of cartridge in the SC242
connector.
table below for states and values for determining the type of cartridge in the SC242
connector.
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
Table 41. Signal Description
(Sheet 6 of 7)
Name
Type
Description
SC242 Occupation Truth Table
Signal
Value
Status
SLOTOCC#
VID[4:0]
VID[4:0]
0
Anything other
than ‘11111’
Anything other
than ‘11111’
Processor with core in SC242 connector.
SLOTOCC#
VID[4:0]
VID[4:0]
0
11111
11111
Terminator cartridge in SC242 connector
(i.e., no core present).
(i.e., no core present).
SLOTOCC#
VID[4:0]
VID[4:0]
1
Any value
Any value
SC242 connector not occupied.