Intel Pentium 4 BX80528JK150GR2 Manual Do Utilizador
Códigos do produto
BX80528JK150GR2
Intel
®
Pentium
®
4 Processor in the 423-pin Package
31
3.0
System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotonicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines or cause
incorrect latching of data. Excessive signal swings (overshoot and undershoot) are detrimental to
silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded.
Additionally, overshoot and undershoot can cause timing degradation due to the build up of inter-
symbol interference (ISI) effects.
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotonicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines or cause
incorrect latching of data. Excessive signal swings (overshoot and undershoot) are detrimental to
silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded.
Additionally, overshoot and undershoot can cause timing degradation due to the build up of inter-
symbol interference (ISI) effects.
For these reasons, it is crucial that the designer work towards a solution that provides acceptable
signal quality across all systematic variations encountered in volume manufacturing.
signal quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation, and all specifications are at the processor silicon and cannot be measured at the
processor pins. The Intel
through simulation, and all specifications are at the processor silicon and cannot be measured at the
processor pins. The Intel
®
Pentium
®
4 Processor Overshoot Checker Tool is to be utilized to
determine pass/fail signal quality conditions found through simulation analysis with the Intel
®
Pentium
®
4 Processor I/O Buffer Models (IBIS format). This tool takes into account the
specifications contained in this section.
Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all system bus AC timing specifications in
Section 2.12. Therefore, proper simulation of the Pentium 4 processor system bus is the only means
to verify proper timing and signal quality metrics, and Intel highly recommends simulation during
system design and measurement during system analysis.
observable through simulation. The same is true for all system bus AC timing specifications in
Section 2.12. Therefore, proper simulation of the Pentium 4 processor system bus is the only means
to verify proper timing and signal quality metrics, and Intel highly recommends simulation during
system design and measurement during system analysis.
3.1
BCLK Signal Quality Specifications and Measurement
Guidelines
Guidelines
Table 16 describes the signal quality specifications for the processor system bus clock (BCLK)
signals. Figure 12 describes the signal quality waveform for the system bus clock at the processor
silicon. Specifications are measured at the processor silicon, not the 423-pin Socket pins.
signals. Figure 12 describes the signal quality waveform for the system bus clock at the processor
silicon. Specifications are measured at the processor silicon, not the 423-pin Socket pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium 4 processor frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
specification is an absolute value.
Table 16. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes
1
BCLK[1:0] Overshoot
N/A
0.30
V
BCLK[1:0] Undershoot
N/A
0.30
V
BCLK[1:0] Ringback Margin
0.20
N/A
V
BCLK[1:0] Threshold Region
N/A
0.10
V
2