Intel Xeon X3460 BX80605X3460 Manual Do Utilizador

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

131

This register maps the error severity detected by the IIO to one of the system events.

This register is used to generate an Intel

®

 Scalable Memory Interconnect (Intel SMI) 

interrupt to the processor by firmware.

This register controls IIO (Integrated I/O) Reset behavior. Any resets produced by a 
write to this register must be delayed until the configuration write is completed on the 
initiating interface (PCI Express, DMI, JTAG).

There is no “SOFT RESET” bit in this register. That function is invoked through the DMI 
interface. There are no Intel

 

QuickPath Interconnect PCI Express gear ratio definitions 

in this register. The Intel

 

QuickPath Interconnect frequencies are specified in the FREQ 

register. The PCI Express frequencies are automatically negotiated in-band.

31:7

RV

0

6:4

RWS

010

Severity 1 Error Map
010 = Generate NMI
001 = Generate SMI
000 = No Inband Message

3

RV

0

2:0

RWS

010

Severity 0 Error Map
010 = Generate NMI
001 = Generate SMI
000 = No Inband Message

31:1

RO

0

0

RWS

0

Generate Intel SMI
When this bit is set and transition from 0 to 1, Integrated I/O dispatches a 

MCA interrupt defined in the error MCA configuration register to the 

processor. This bit is cleared by hardware when Integrated I/O has 

dispatched MCA to the Intel QuickPath Interconnect link.
This bit should never be set since the processor does not support MCA