Intel Xeon X3460 BX80605X3460 Manual Do Utilizador
Códigos do produto
BX80605X3460
Processor Uncore Configuration Registers
206
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
27:26
RO
0
Reserved
25:24
RW
0
PAM3_LOENABLE
0D0000h–0D3FFFh Attribute (LOENABLE) This field controls the steering of
0D0000h–0D3FFFh Attribute (LOENABLE) This field controls the steering of
read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
23:22
RO
0
Reserved
21:20
RW
0
PAM2_HIENABLE
0CC000h–0CFFFFh Attribute (HIENABLE) This field controls the steering of
0CC000h–0CFFFFh Attribute (HIENABLE) This field controls the steering of
read and write cycles that address the BIOS area from 0CC000h to 0CFFFFh.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
19:18
RO
0
Reserved
17:16
RW
0
PAM2_LOENABLE
0C8000h–0CBFFFhAttribute (LOENABLE) This field controls the steering of
0C8000h–0CBFFFhAttribute (LOENABLE) This field controls the steering of
read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
35:14
RO
0
Reserved
13:12
RW
0
PAM1_HIENABLE
0C4000h–0C7FFFh Attribute (HIENABLE) This field controls the steering of
0C4000h–0C7FFFh Attribute (HIENABLE) This field controls the steering of
read and write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
11:10
RO
0
Reserved
9:8
RW
0
PAM1_LOENABLE
0C0000h–0C3FFFh Attribute (LOENABLE) This field controls the steering of
0C0000h–0C3FFFh Attribute (LOENABLE) This field controls the steering of
read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
7:6
RO
0
Reserved
5:4
RW
0
PAM0_HIENABLE
0F0000h–0FFFFFh Attribute (HIENABLE) This field controls the steering of read
0F0000h–0FFFFFh Attribute (HIENABLE) This field controls the steering of read
and write cycles that address the BIOS area from 0F0000h to 0FFFFFh.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.
3:0
RO
0
Reserved
Device:
0
Function: 1
Offset:
40h
Access as a DWord
Bit
Attr
Default
Description