Infineon HYB39S256400CT-7.5 Manual Do Utilizador
INFINEON Technologies
1
8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
256MBit Synchronous DRAM
256 MBit Synchronous DRAM
The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.17
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.17
µ
m 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
•
High Performance:
•
Fully Synchronous to Positive Clock Edge
•
0 to 70
°
C operating temperature
•
Four Banks controlled by BA0 & BA1
•
Programmable CAS Latency: 2 & 3
•
Programmable Wrap Sequence: Sequential
or Interleave
or Interleave
•
Programmable Burst Length:
1, 2, 4, 8
1, 2, 4, 8
•
Full page burst length (optional) for
sequential wrap around
sequential wrap around
-7.5
-8
-8A
Units
fCK
133
125
125
MHz
tCK3
7.5
8
8
ns
tAC3
5.4
6
6
ns
tCK2
10
10
12
ns
tAC2
6
6
6
ns
•
Multiple Burst Read with Single Write
Operation
Operation
•
Automatic and Controlled Precharge
Command
Command
•
Data Mask for Read / Write control (x4, x8)
•
Data Mask for byte control (x16)
•
Auto Refresh (CBR) and Self Refresh
•
Power Down and Clock Suspend Mode
•
8192 refresh cycles / 64 ms (7,8
µ
s)
•
Random Column Address every CLK
( 1-N Rule)
( 1-N Rule)
•
Single 3.3V +/- 0.3V Power Supply
•
LVTTL Interface versions
•
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
P-TSOPII-54 400mil width (x4, x8, x16)
•
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
-8A parts for PC100 3-2-2 operation
-8 parts for PC100 2-2-2 operation
-8A parts for PC100 3-2-2 operation