Cisco Cisco UCS B440 M1 High-Performance Blade Server Guia De Resolução De Problemas
Error Correcting Codes
UCS Enhanced Memory Error Management
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Error Correcting Codes
Traditional “SECDED” Error Correcting Codes
ECC codes on memory systems are traditionally applied across 64 bit (8-byte) data words protected by 8 check
bits, to form a 72-bit code word. Such Single Error Correct, Double Error Detect (SECDED) ECC codes could
correct any single bit error, and detect any double bit error. Through the use of Intel’s Xeon processors, Cisco’s
UCS systems enhance the traditional SECDED features with more advanced error correction mechanisms such as
those listed below.
bits, to form a 72-bit code word. Such Single Error Correct, Double Error Detect (SECDED) ECC codes could
correct any single bit error, and detect any double bit error. Through the use of Intel’s Xeon processors, Cisco’s
UCS systems enhance the traditional SECDED features with more advanced error correction mechanisms such as
those listed below.
UCS Error Detection and Correction
UCS servers built from Intel Xeon “EP” class processors employ ECC codes that not only correct any single bit
error, but can also correct any number of errors that are confined to a single x4 DRAM chip, and detect errors in up
to 2 devices. This capability is known as Single Device Data Correction (SDDC). Additionally, when operating in
lockstep mode, which spreads the ECC code words across a pair of memory channels, SDDC is extended to correct
errors in any x8 bit DRAM chip (or adjacent pair of x4 DRAM chips). To provide even higher levels of reliability and
availability, UCS servers built from Xeon “EX” class processors can correct errors in any (not necessarily adjacent)
pair of x4 devices, and detect errors in up to 3 devices. This capability is known as Double Device Data Correction
(DDDC).
error, but can also correct any number of errors that are confined to a single x4 DRAM chip, and detect errors in up
to 2 devices. This capability is known as Single Device Data Correction (SDDC). Additionally, when operating in
lockstep mode, which spreads the ECC code words across a pair of memory channels, SDDC is extended to correct
errors in any x8 bit DRAM chip (or adjacent pair of x4 DRAM chips). To provide even higher levels of reliability and
availability, UCS servers built from Xeon “EX” class processors can correct errors in any (not necessarily adjacent)
pair of x4 devices, and detect errors in up to 3 devices. This capability is known as Double Device Data Correction
(DDDC).