Intel AT80604004872AA Manual Do Utilizador
Intel® Xeon® Processor 7500 Datasheet, Volume 1
111
Signal Definitions
SMBCLK
I/O
The SMBus Clock (SMBCLK) signal is an input clock to the system management logic
which is required for operation of the system management features of the Intel®
Xeon® processor 7500 series. This clock is driven by the SMBus controller and is
asynchronous to other clocks in the processor. This is an open drain signal.
SMBDAT
I/O
The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus devices.
This is an open drain signal.
SPDCLK
I/O
This is a bi-directional clock signal between Intel® Xeon® processor 7500 series,
DRAM SPD registers and external components on the board. This is an open drain
signal.
SPDDAT
I/O
This is a bi-directional data signal between Intel® Xeon® processor 7500 series,
DRAM SPD registers and external components on the board. This is an open drain
signal.
SYSCLK_DP/SYSCLK_DP
I
The differential clock pair SYSCLK_DP/SYSCLK_DN provides the fundamental clock
source for the Intel® Xeon® processor 7500 series. All processor link agents must
receive these signals to drive their outputs and latch their inputs. All external timing
parameters are specified with respect to the rising edge of SYSCLK crossing the
falling edge of SYSCLK_N. These differential clock pair should not be asserted until
VCCCORE, VIOC, VIOF, VCACHE and VCC33 are stabilized.
SYSCLK_LAI/SYSCLK_LAI_N
I
These are reference clocks used only for debug purposes. Electrical specifications on
these clocks are identical to SYSCLK_DP/SYSCLK_DN.
TCK
I
Test Clock (TCK) provides the clock input for the processor TAP.
TDI
I
Test Data In (TDI) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
Test Data Out (TDO) transfers serial test data out of the processor. TDO provides the
serial output needed for JTAG specification support. This is an open drain output.
TEST[3:0]
I
Four corner pins used to study socket corner joint reliability. VSS on package,
however, not required to be connected.
Test-Hi
I
Strap pins to VIO via resistor.
THERMALERT_N
O
Thermal Alert (THERMALERT_N) is an output signal and is asserted when the on-die
thermal sensors readings exceed a pre-programmed threshold.
THERMTRIP_N
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. To ensure that there are no false trips, Thermal Trip (THERMTRIP_N)
will activate at a temperature that is about 115°C as measured at the core. Once
activated, the processor will stop all execution and the signal remains latched until
RESET_N goes active. It is strongly recommended that all power be removed from
the processor before bringing the processor back up. If the temperature has not
dropped below the trip level, the processor will continue to drive THERMTRIP_N and
remain stopped. Strapping is 1k-10k Ohms.
TMS
I
Test Mode Select (TMS) is a JTAG specification support signal used by debug tools.
TRST_N
I
Test Reset (TRST_N) resets the TAP logic. TRST_N must be driven electrically low
during power on Reset.
VCACHE
I
This provides power to processor LLC and system interface logic. Actual value of the
voltage is determined by the settings of CVID[7:1].
VCACHESENSE
IO
VR Sense lines. (VCACHE)
VCC33
I
VCC33 supplies 3.3V to PIROM/OEM Scratch ROM, INITROM and level translators.
This supply is required both for PIROM usage and for correct processor boot
operation.
VCCCORE
I
This provides power to the Cores on the processor. Actual value of the voltage is
determined by the settings of VID[7:0].
VSSCOREESENSE
IO
VR Sense lines. (Vcore)
Table 5-1.
Signal Definitions (Sheet 5 of 6)
Name
Type
Description