Intel Itanium 9140M NE80567KF028009 Manual Do Utilizador
Códigos do produto
NE80567KF028009
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
31
Electrical Specifications
2.7
System Bus Clock and Processor Clocking
The BCLKn and BCLKp inputs control the operating frequency of the processor system
bus interface. All processor system bus timing parameters are specified with respect to
the falling edge of BCLKn and rising edge of BCLKp. The address pins A[21:17]# will be
used to specify the system bus frequency during reset. The processor will ensure that
the correct bus/core ratio is elected based on the bus frequency that is specified during
reset.
bus interface. All processor system bus timing parameters are specified with respect to
the falling edge of BCLKn and rising edge of BCLKp. The address pins A[21:17]# will be
used to specify the system bus frequency during reset. The processor will ensure that
the correct bus/core ratio is elected based on the bus frequency that is specified during
reset.
Cold Reset Sequence:
• The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
• RESET# must be asserted before PWRGOOD is asserted.
• The duration from the assertion of PWRGOOD to the deassertion of RESET# must
• The duration from the assertion of PWRGOOD to the deassertion of RESET# must
be 1 millisecond minimum.
• After RESET# is deasserted, all the configuration, including pins A[21:17]#, must
remain valid for 2 BCLKs (minimum) to 3 BCLKs (maximum).
• BCLK is shown as a time reference to the BCLK period. It is not a requirement that
this is BCLKn or BCLKp signal.
• Configuration signals other than A[21:17]# must be asserted 4 BCLKs prior to the
deasserted edge of RESET# and must remain valid for 2 BCLKs (minimum) to 3
BCLKs (maximum) after the deasserted edge of RESET#.
BCLKs (maximum) after the deasserted edge of RESET#.
outlines the timing relationship between the configuration pins, RESET# and
PWRGOOD for cold reset.
Figure 2-5. System Bus Reset and Configuration Timings for Cold Reset
000859b
BCLK
PWRGOOD
RESET#
Bus Ratio
(A[21:17]#)
T
A
= 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
T
B
= 1 ms minimum for cold reset
T
D
= 2 BCLKs minimum, 3 BCLKs maximum
T
E
= 4 BCLKs minimum
T
F
= 2 BCLKs minimum, 3 BCLKs maximum
Additional
Configuration
Signals
T
B
T
D
T
E
T
F
T
A
t
1
t
2
t
3
T
C
T
C
= Bus ratio signals must be asserted no later than RESET#
t
-2
t
-1
t
0
t
-4
t
-3