Intel i7-660LM CN80617004857AA Manual Do Utilizador
Códigos do produto
CN80617004857AA
Interfaces
24
Datasheet
2.1.5.2
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back-to-back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6
DRAM Clock Generation
Every supported SO-DIMM has two differential clock pairs. There are total of four clock
pairs driven directly by the processor to two SO-DIMMs.
2.1.7
System Memory Pre-Charge Power Down Support Details
The IMC supports and enables slow exit DDR3 DRAM Device pre-charge power down
DLL control. During a pre-charge power down, a slow exit is where the DRAM device
DLL is disabled after entering pre-charge power down for potential power savings.
2.2
PCI Express Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The processor
has one PCI Express controller that can support one external x16 PCI
Express Graphics Device. The primary PCI Express Graphics port is referred to as
PEG 0.
2.2.1
PCI Express Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI
Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250 MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s.
The PCI Express architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to
for the PCI Express Layering Diagram.