Cisco Cisco Packet Data Gateway (PDG) Manual De Manutenção
New Feature Summary
Generally Available 06-30-2010
1-8
Common Features in Release 8.3
This section provides information on new features that are common to all products in
Release 8.3.
Release 8.3.
Packet Services Card 2
The Packet Services Card 2 (PSC2) is the next-generation packet forwarding card for the
ST40. The PSC2 provides increased aggregate throughput and performance, and a higher
number of subscriber sessions.
ST40. The PSC2 provides increased aggregate throughput and performance, and a higher
number of subscriber sessions.
The PSC2 has been enhanced with a faster network processor unit, featuring two quad-core
Intel x86 2.5Ghz CPUs, 32 GB of RAM. The PSC2 provides 2 to 2.7 times the data
throughput of the original PSC, and the switch fabric interface has been doubled.
Intel x86 2.5Ghz CPUs, 32 GB of RAM. The PSC2 provides 2 to 2.7 times the data
throughput of the original PSC, and the switch fabric interface has been doubled.
A second-generation data transport fixed programmable gate array (DT2 FPGA,
abbreviated as DT2) connects the PSC2’s NPU bus to the switch fabric interface. The
FPGA also provides a bypass path between the line card or Redundancy Crossbar Card
(RCC) and the switch fabric for ATM traffic. Traffic from the line cards or the RCC is
received over the FPGA’s serial links and is sent to the NPU on its switch fabric interface.
The traffic destined for the line cards or RCC is diverted from the NPU interface and sent
over the serial links.
abbreviated as DT2) connects the PSC2’s NPU bus to the switch fabric interface. The
FPGA also provides a bypass path between the line card or Redundancy Crossbar Card
(RCC) and the switch fabric for ATM traffic. Traffic from the line cards or the RCC is
received over the FPGA’s serial links and is sent to the NPU on its switch fabric interface.
The traffic destined for the line cards or RCC is diverted from the NPU interface and sent
over the serial links.
DT2 FPGA also connects to the control processors subsystem via a PCI-E bus. The PCI-E
interface allows the control processors to perform register accesses to the FPGA and some
components attached to it, and also allows DMA operations between the NPU and the
control processors’ memory. A statistics engine is provided in the FPGA. Two reduced
latency DRAM (RLDRAM) chips attached to the FPGA provide 64MB of storage for
counters.
interface allows the control processors to perform register accesses to the FPGA and some
components attached to it, and also allows DMA operations between the NPU and the
control processors’ memory. A statistics engine is provided in the FPGA. Two reduced
latency DRAM (RLDRAM) chips attached to the FPGA provide 64MB of storage for
counters.
The PSC2 has a 2.5 G/bps-based security processor that provides the highest performance
for cryptographic acceleration of next-generation IP Security (IPsec), Secure Sockets Layer
(SSL) and wireless LAN/WAN security applications with the latest security algorithms.
for cryptographic acceleration of next-generation IP Security (IPsec), Secure Sockets Layer
(SSL) and wireless LAN/WAN security applications with the latest security algorithms.
Interoperability
It is not recommended that PSC2s are mixed with PSCs, since this prevents the PSC2 from
operating at its full potential. Due to the different processor speeds and memory
configurations, the PSC2 cannot be combined in a chassis with the original PSC 16 GB.
operating at its full potential. Due to the different processor speeds and memory
configurations, the PSC2 cannot be combined in a chassis with the original PSC 16 GB.
For more information, see the “Hardware Platform Overview” chapter of the Hardware
Installation and Administration Guide.
Installation and Administration Guide.