ASUS kn97x Manual Do Utilizador
ASUS KN97-X User’s Manual
46
IV. BIOS SOFTWARE
IV
. BIOS
(Chipset Features)
Chipset Features Setup
This “Chipset Features Setup” option controls the configuration of the board’s chipset.
Control keys for this screen are the same as for the previous screen.
Control keys for this screen are the same as for the previous screen.
NOTE: SETUP Defaults are noted in parenthesis next to each function heading.
Details of Chipset Features Setup
Auto Configuration (60ns DRAM)
The default setting of 60ns DRAM sets the optimal timings for items 2 through 6 for
60ns DRAM modules. If you are using 70ns DRAM modules, you must change this
item to 70ns DRAM. See section III for DRAM installation information.
DRAM Refresh Type (RAS Only)
Leave on default setting of RAS Only as this is the current standard.
CPU-to-PCI IDE Posting (Enabled)
Leave on default setting of Enabled so that the CPU to PCI IDE posting cycles are
treated as normal I/O write transactions.
USWC Write Posting (Enabled)
Leave on default setting of Enabled to allow USWC write posting during
I/O bridge access.
CPU-to-PCI Write Post (Enabled)
The default setting of Enabled will increase the efficiency of the PCI bus and speed
up the execution in the processor.
PCI-to-DRAM Pipeline (Enabled)
The default of Enabled will increase the bandwidth of the path between the
PCI and the DRAM to enhance the PCI bus efficiency and DRAM accessing.
PCI Burst Write Combining (Enabled)
The default setting of Enabled will increase the efficiency of PCI bus by combining
several CPU to PCI write cycles into one. VGA performance is increased by this
action.
The default setting of 60ns DRAM sets the optimal timings for items 2 through 6 for
60ns DRAM modules. If you are using 70ns DRAM modules, you must change this
item to 70ns DRAM. See section III for DRAM installation information.
DRAM Refresh Type (RAS Only)
Leave on default setting of RAS Only as this is the current standard.
CPU-to-PCI IDE Posting (Enabled)
Leave on default setting of Enabled so that the CPU to PCI IDE posting cycles are
treated as normal I/O write transactions.
USWC Write Posting (Enabled)
Leave on default setting of Enabled to allow USWC write posting during
I/O bridge access.
CPU-to-PCI Write Post (Enabled)
The default setting of Enabled will increase the efficiency of the PCI bus and speed
up the execution in the processor.
PCI-to-DRAM Pipeline (Enabled)
The default of Enabled will increase the bandwidth of the path between the
PCI and the DRAM to enhance the PCI bus efficiency and DRAM accessing.
PCI Burst Write Combining (Enabled)
The default setting of Enabled will increase the efficiency of PCI bus by combining
several CPU to PCI write cycles into one. VGA performance is increased by this
action.