CyberResearch PCIDIO 96H Manual Do Utilizador

34

• C/C++ Libraries

PCI_CH0_PA: CH1’s Port A

PCI_CH0_PB: CH1’s Port B

PCI_CH0_PC: CH1’s Port C

PCI_CH0_PCU: CH1’s Port C Upper Nibble

PCI_CH0_PCL: CH1’s Port C Low Nibble

PCI_CH1_PA: CH2’s Port A

PCI_CH1_PB: CH2’s Port B

PCI_CH1_PC: CH2’s Port C

PCI_CH1_PCU: CH2’s Port C Upper Nibble

PCI_CH1_PCL: CH2’s Port C Low Nibble

PCI_CH2_PA: CH2’s Port A

PCI_CH2_PB: CH2’s Port B

PCI_CH2_PC: CH2’s Port C

PCI_CH2_PCU: CH2’s Port C Upper Nibble

PCI_CH2_PCL: CH2’s Port C Low Nibble

PCI_CH3_PA: CH3’s Port A

PCI_CH3_PB: CH3’s Port B

PCI_CH3_PC: CH3’s Port C

PCI_CH3_PCU: CH3’s Port C Upper Nibble

PCI_CH3_PCL: CH3’s Port C Low Nibble

PCI_CH0_PAE: CH1’s Port A uses External

Latch

PCI_CH0_PBE: CH1’s Port B uses External

Latch

PCI_CH0_PCE: CH1’s Port C uses External

Latch

PCI_CH1_PAE: CH2’s Port A uses External

Latch

PCI_CH1_PBE: CH2’s Port B uses External

Latch

PCI_CH1_PCE: CH2’s Port C uses External

Latch

Note: 1.CH2 and CH3 are only available for

PCIDIO 96H

.

2.Only CH0 is available for

PCIDIO 24H

.

@ Return Code

ERR_NoError