Intel BX80635E52697V2 Manual Do Utilizador

 

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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

Datasheet Volume One of Two

• Memory thermal monitoring support for DIMM temperature via two memory 

signals, MEM_HOT_C{01/23}_N

• The PCI Express* port(s) are fully-compliant to the PCI Express* Base 

• Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)
• Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* 

devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports

• 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0), 

also can be downgraded to x2 or x1

• Negotiating down to narrower widths is supported, see 

— x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1. 
— x8 port (Port 1) may negotiate down to x4, x2, or x1. 
— x4 port (Port 0) may negotiate down to x2, or x1. 
— When negotiating down to narrower widths, there are caveats as to how lane 

reversal is supported.

• Non-Transparent Bridge (NTB) is supported by PCIe Port3a/IOU1. For more details 

on NTB mode operation refer to PCI Express Base Specification - Revision 3.0:

— x4, x8 or x16 widths and at PCIe* 1.0, 2.0, 3.0 speeds
— Two usage models; NTB attached to a Root Port or NTB attached to another 

NTB

— Supports three 64-bit BARs
— Supports posted writes and non-posted memory read transactions across the 

NTB

— Supports INTx, MSI and MSI-X mechanisms for interrupts on both side of NTB 

in upstream direction only

• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration 

space aliases directly to the PCI compatibility configuration space. The remaining 
portion of the fixed 4-KB block of memory-mapped space above that (starting at 
100h) is known as extended configuration space.

• PCI Express* Enhanced Access Mechanism. Accessing the device configuration 

space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset.
• Supports receiving and decoding 64 bits of address from PCI Express*.

— Memory transactions received from PCI Express* that go above the top of 

physical address space (when Intel VT-d is enabled, the check would be against 

the translated HPA (Host Physical Address) address) are reported as errors by 

the processor. 

— Outbound access to PCI Express* will always have address bits 63 to 46 

cleared.

• Re-issues Configuration cycles that have been previously completed with the 

Configuration Retry status.