Intel BX80635E52697V2 Manual Do Utilizador

 

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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 

Datasheet Volume One of Two

The DDR3 power states can be summarized as the following:

• Normal operation (highest power consumption).
• CKE Power-Down: Opportunistic, per rank control after idle time. There may be 

different levels.

— Active  Power-Down.
— Precharge Power-Down with Fast Exit.
— Precharge power Down with Slow Exit.

• Self Refresh: In this mode no transaction is executed. The DDR consumes the 

minimum possible power.

The CKE input land is used to enter and exit different power-down modes. The memory 

controller has a configurable activity timeout for each rank. Whenever no reads are 

present to a given rank for the configured interval, the memory controller will transition 
the rank to power-down mode.

The memory controller transitions the DRAM to power-down by de-asserting CKE and 

driving a NOP command. The memory controller will tri-state all DDR interface lands 
except CKE (de-asserted) and ODT while in power-down. The memory controller will 

transition the DRAM out of power-down state by synchronously asserting CKE and 

driving a NOP command.

When CKE is off the internal DDR clock is disabled and the DDR power is significantly 

reduced.

The DDR defines three levels of power-down:

• Active power-down: This mode is entered if there are open pages when CKE is de-

asserted. In this mode the open pages are retained. Existing this mode is 3 - 5 
DCLK cycles.

• Precharge power-down fast exit: This mode is entered if all banks in DDR are 

precharged when de-asserting CKE. Existing this mode is 3 - 5 DCLK cycles. 

Difference from the active power-down mode is that when waking up all page-
buffers are empty.

130W 1S WS (4-cores)

175

115W (12/10-cores)

180

95W (10/8-cores)

150

95W (6/4-cores)

130

80W (6/4-cores)

110

70W (10-cores)

120

60W (6-cores)

100

LV95W (10-cores)

150

LV70W (10/8-cores)

120

LV50W (6-cores)

75