IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction-Cache and Data-Cache Operation
Page 132 of 377
gx_03.fm.(1.2)
March 27, 2006
3.4.1.1 Data-Cache Flash Invalidation
The data cache is automatically invalidated when the 750GX is powered up and during a hard reset.
However, a soft reset does not automatically invalidate the data cache. Software must use the HID0 data-
cache flash invalidate bit (HID0[DCFI]) if data cache invalidation is desired after a soft reset. Once
HID0[DCFI] is set through an mtspr operation, the 750GX automatically clears this bit in the next clock cycle
(provided that the data cache is enabled in the HID0 Register).
However, a soft reset does not automatically invalidate the data cache. Software must use the HID0 data-
cache flash invalidate bit (HID0[DCFI]) if data cache invalidation is desired after a soft reset. Once
HID0[DCFI] is set through an mtspr operation, the 750GX automatically clears this bit in the next clock cycle
(provided that the data cache is enabled in the HID0 Register).
Note that some PowerPC microprocessors accomplish data-cache flash invalidation by setting and clearing
HID0[DCFI] with two consecutive mtspr instructions (that is, the bit is not automatically cleared by the micro-
processor). Software that has this sequence of operations does not need to be changed to run on the 750GX.
HID0[DCFI] with two consecutive mtspr instructions (that is, the bit is not automatically cleared by the micro-
processor). Software that has this sequence of operations does not need to be changed to run on the 750GX.
3.4.1.2 Enabling and Disabling the Data Cache
The data cache can be enabled or disabled by using the data-cache enable bit, HID0[DCE]. HID0[DCE] is
cleared on power-up, disabling the data cache.
cleared on power-up, disabling the data cache.
When the data cache is in the disabled state (HID0[DCE] = 0), the cache tag state bits are ignored, and all
accesses are propagated to the L2 cache or 60x bus as single-beat transactions. Note that the CI (cache
inhibit) signal always reflects the state of the caching-inhibited memory/cache access attribute (the I bit) inde-
pendent of the state of HID0[DCE]. Also note that disabling the data cache does not affect the translation
logic; translation for data accesses is controlled by MSR[DR].
accesses are propagated to the L2 cache or 60x bus as single-beat transactions. Note that the CI (cache
inhibit) signal always reflects the state of the caching-inhibited memory/cache access attribute (the I bit) inde-
pendent of the state of HID0[DCE]. Also note that disabling the data cache does not affect the translation
logic; translation for data accesses is controlled by MSR[DR].
The setting of the DCE bit must be preceded by a synchronization (sync) instruction to prevent the cache
from being enabled or disabled in the middle of a data access. In addition, the cache must be globally flushed
before it is disabled to prevent coherency problems when it is re-enabled.
from being enabled or disabled in the middle of a data access. In addition, the cache must be globally flushed
before it is disabled to prevent coherency problems when it is re-enabled.
Snooping is not performed when the data cache is disabled.
The Data Cache Block Set to Zero (dcbz) instruction will cause an alignment exception when the data cache
is disabled. The touch load (Data Cache Block Touch [dcbt] and Data Cache Block Touch for Store [dcbtst]
instructions are no-ops when the data cache is disabled. Other cache operations (caused by the Data Cache
Block Flush (dcbf), Data Cache Block Store [dcbst], and Data Cache Block Invalidate [dcbi] instructions) are
not affected by disabling the cache. This can potentially cause coherency errors. For example, a dcbf instruc-
tion that hits a modified cache block in the disabled cache will cause a copyback to memory of potentially
stale data.
is disabled. The touch load (Data Cache Block Touch [dcbt] and Data Cache Block Touch for Store [dcbtst]
instructions are no-ops when the data cache is disabled. Other cache operations (caused by the Data Cache
Block Flush (dcbf), Data Cache Block Store [dcbst], and Data Cache Block Invalidate [dcbi] instructions) are
not affected by disabling the cache. This can potentially cause coherency errors. For example, a dcbf instruc-
tion that hits a modified cache block in the disabled cache will cause a copyback to memory of potentially
stale data.
3.4.1.3 Locking the Data Cache
The contents of the data cache can be locked by setting the data-cache lock bit, HID0[DLOCK]. A data
access that hits in a locked data cache is serviced by the cache. However, all accesses that miss in the
locked cache are propagated to the L2 cache or 60x bus as single-beat transactions. Note that the CI signal
always reflects the state of the caching-inhibited memory/cache access attribute (the I bit) independent of the
state of HID0[DLOCK].
access that hits in a locked data cache is serviced by the cache. However, all accesses that miss in the
locked cache are propagated to the L2 cache or 60x bus as single-beat transactions. Note that the CI signal
always reflects the state of the caching-inhibited memory/cache access attribute (the I bit) independent of the
state of HID0[DLOCK].
The 750GX treats snoop hits to a locked data cache the same as snoop hits to an unlocked data cache.
However, any cache block invalidated by a snoop hit remains invalid until the cache is unlocked.
However, any cache block invalidated by a snoop hit remains invalid until the cache is unlocked.
The setting of the DLOCK bit must be preceded by a sync instruction to prevent the data cache from being
locked during a data access.
locked during a data access.