IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_03.fm.(1.2)
March 27, 2006
March 27, 2006
Instruction-Cache and Data-Cache Operation
Page 135 of 377
For this reason, avoid using dcbz for data that is shared in real time and that is not protected during writing
through higher-level software synchronization protocols (such as semaphores). Use of dcbz must be avoided
for managing semaphores themselves. An alternative solution could be to prevent dcbz from hitting in the L1
cache by performing a dcbf to that address beforehand.
through higher-level software synchronization protocols (such as semaphores). Use of dcbz must be avoided
for managing semaphores themselves. An alternative solution could be to prevent dcbz from hitting in the L1
cache by performing a dcbf to that address beforehand.
3.4.2.3 Data Cache Block Store (dcbst)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC Architecture. This instruction is treated as a load with respect to address translation and memory
protection.
PowerPC Architecture. This instruction is treated as a load with respect to address translation and memory
protection.
If the address hits in the cache and the cache block is in the exclusive (E) state, no action is taken. If the
address hits in the cache and the cache block is in the modified (M) state, the modified block is written back to
memory and the cache block is placed in the exclusive (E) state.
address hits in the cache and the cache block is in the modified (M) state, the modified block is written back to
memory and the cache block is placed in the exclusive (E) state.
The execution of a dcbst instruction does not broadcast on the 60x bus unless broadcast is enabled through
the HID0[ABE] bit. The function of this instruction is independent of the WIMG bit settings of the block
containing the effective address. The dcbst instruction executes regardless of whether the cache is disabled
or locked; however, a BAT or TLB protection violation generates a DSI exception.
the HID0[ABE] bit. The function of this instruction is independent of the WIMG bit settings of the block
containing the effective address. The dcbst instruction executes regardless of whether the cache is disabled
or locked; however, a BAT or TLB protection violation generates a DSI exception.
3.4.2.4 Data Cache Block Flush (dcbf)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC Architecture. This instruction is treated as a load with respect to address translation and memory
protection.
PowerPC Architecture. This instruction is treated as a load with respect to address translation and memory
protection.
If the address hits in the cache, and the block is in the modified (M) state, the modified block is written back to
memory and the cache block is placed in the invalid (I) state. If the address hits in the cache, and the cache
block is in the exclusive (E) state, the cache block is placed in the invalid (I) state. If the address misses in the
cache, no action is taken.
memory and the cache block is placed in the invalid (I) state. If the address hits in the cache, and the cache
block is in the exclusive (E) state, the cache block is placed in the invalid (I) state. If the address misses in the
cache, no action is taken.
The execution of dcbf does not broadcast on the 60x bus unless broadcast is enabled through the
HID0[ABE] bit. The function of this instruction is independent of the WIMG bit settings of the block containing
the effective address. The dcbf instruction executes regardless of whether the cache is disabled or locked.
However, a BAT or TLB protection violation generates a DSI exception.
HID0[ABE] bit. The function of this instruction is independent of the WIMG bit settings of the block containing
the effective address. The dcbf instruction executes regardless of whether the cache is disabled or locked.
However, a BAT or TLB protection violation generates a DSI exception.
3.4.2.5 Data Cache Block Invalidate (dcbi)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC Architecture. This instruction is treated as a store with respect to address translation and memory
protection.
PowerPC Architecture. This instruction is treated as a store with respect to address translation and memory
protection.
If the address hits in the cache, the cache block is placed in the invalid (I) state, regardless of whether the
data is modified. Because this instruction can effectively destroy modified data, it is privileged (that is, dcbi is
available to programs at the supervisor privilege level, MSR[PR] = 0). The execution of dcbi does not broad-
cast on the 60x bus unless broadcast is enabled through the HID0[ABE] bit. The function of this instruction is
independent of the WIMG bit settings of the block containing the effective address. The dcbi instruction
executes regardless of whether the cache is disabled or locked. However, a BAT or TLB protection violation
generates a DSI exception.
data is modified. Because this instruction can effectively destroy modified data, it is privileged (that is, dcbi is
available to programs at the supervisor privilege level, MSR[PR] = 0). The execution of dcbi does not broad-
cast on the 60x bus unless broadcast is enabled through the HID0[ABE] bit. The function of this instruction is
independent of the WIMG bit settings of the block containing the effective address. The dcbi instruction
executes regardless of whether the cache is disabled or locked. However, a BAT or TLB protection violation
generates a DSI exception.