IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Page 22 of 377
gx_preface.fm.(1.2)
March 27, 2006
Using This Manual with the Programming Environments Manual
Because the PowerPC Architecture is designed to be flexible to support a broad range of processors, the
PowerPC Microprocessor Family: The Programming Environments Manual provides a general description of
features that are common to PowerPC processors and indicates those features that are optional or that might
be implemented differently in the design of each processor.
PowerPC Microprocessor Family: The Programming Environments Manual provides a general description of
features that are common to PowerPC processors and indicates those features that are optional or that might
be implemented differently in the design of each processor.
This document and The Programming Environments Manual describe three levels, or programming environ-
ments, of the PowerPC Architecture:
ments, of the PowerPC Architecture:
• PowerPC user instruction set architecture (UISA)—The UISA defines the level of the architecture to
which user-level software should conform. The UISA defines the base user-level instruction set, user-
level registers, data types, memory conventions, and the memory and programming models seen by
application programmers.
level registers, data types, memory conventions, and the memory and programming models seen by
application programmers.
• PowerPC virtual environment architecture (VEA)—The VEA, which is the smallest component of the
PowerPC Architecture, defines additional user-level functionality that falls outside typical user-level soft-
ware requirements. The VEA describes the memory model for an environment in which multiple proces-
sors or other devices can access external memory and defines aspects of the cache model and cache-
control instructions from a user-level perspective. The resources defined by the VEA are particularly use-
ful for optimizing memory accesses and for managing resources in an environment in which other proces-
sors and other devices can access external memory.
ware requirements. The VEA describes the memory model for an environment in which multiple proces-
sors or other devices can access external memory and defines aspects of the cache model and cache-
control instructions from a user-level perspective. The resources defined by the VEA are particularly use-
ful for optimizing memory accesses and for managing resources in an environment in which other proces-
sors and other devices can access external memory.
Implementations that conform to the PowerPC VEA also conform to the PowerPC UISA, but might not
necessarily adhere to the OEA.
necessarily adhere to the OEA.
• PowerPC operating environment architecture (OEA)—The OEA defines supervisor-level resources typi-
cally required by an operating system. The OEA defines the PowerPC memory-management model,
supervisor-level registers, and the exception model.
supervisor-level registers, and the exception model.
Implementations that conform to the PowerPC OEA also conform to the PowerPC UISA and VEA.
Some resources are defined more generally at one level in the architecture and more specifically at another.
For example, conditions that cause a floating-point exception are defined by the UISA, while the exception
mechanism itself is defined by the OEA.
For example, conditions that cause a floating-point exception are defined by the UISA, while the exception
mechanism itself is defined by the OEA.
Because it is important to distinguish between the levels of the architecture in order to ensure compatibility
across multiple platforms, those distinctions are shown clearly throughout this book.
across multiple platforms, those distinctions are shown clearly throughout this book.
For ease in reference, the arrangement of topics in this book follows that of The Programming Environments
Manual. Topics build upon one another, beginning with a description and complete summary of 750GX-
specific registers and instructions and progressing to more specialized topics such as 750GX-specific details
regarding the cache, exception, and memory-management models. Therefore, chapters can include informa-
tion from multiple levels of the architecture. (For example, the discussion of the cache model uses information
from both the VEA and the OEA.)
Manual. Topics build upon one another, beginning with a description and complete summary of 750GX-
specific registers and instructions and progressing to more specialized topics such as 750GX-specific details
regarding the cache, exception, and memory-management models. Therefore, chapters can include informa-
tion from multiple levels of the architecture. (For example, the discussion of the cache model uses information
from both the VEA and the OEA.)
The PowerPC Architecture: A Specification for a New Family of RISC Processors defines the architecture
from the perspective of the three programming environments and remains the defining document for the
PowerPC Architecture. For information about PowerPC documentation, see Related Publications on
page 19.
from the perspective of the three programming environments and remains the defining document for the
PowerPC Architecture. For information about PowerPC documentation, see Related Publications on
page 19.