IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 308 of 377
gx_08.fm.(1.2)
March 27, 2006
Note: TEA generates a machine-check exception depending on MSR[ME]. Clearing the machine-check-
exception enable control bits leads to a true checkstop condition (instruction execution halted and processor
clock stopped).
exception enable control bits leads to a true checkstop condition (instruction execution halted and processor
clock stopped).
8.4.5 Memory Coherency—MEI Protocol
The 750GX provides dedicated hardware to provide memory coherency by snooping bus transactions. The
address retry capability enforces the 3-state, MEI cache-coherency protocol (see Figure 8-16 on page 309).
address retry capability enforces the 3-state, MEI cache-coherency protocol (see Figure 8-16 on page 309).
The global (GBL) output signal indicates whether the current transaction must be snooped by other snooping
devices on the bus. Address-bus masters assert GBL to indicate that the current transaction is a global
access (that is, an access to memory shared by more than one device). If GBL is not asserted for the transac-
tion, that transaction is not snooped. When other devices detect the GBL input asserted, they must respond
by snooping the broadcast address.
devices on the bus. Address-bus masters assert GBL to indicate that the current transaction is a global
access (that is, an access to memory shared by more than one device). If GBL is not asserted for the transac-
tion, that transaction is not snooped. When other devices detect the GBL input asserted, they must respond
by snooping the broadcast address.
Normally, GBL reflects the M bit value specified for the memory reference in the corresponding translation
descriptors. Note that care must be taken to minimize the number of pages marked as global, because the
retry protocol discussed in the previous section is used to enforce coherency and can require significant bus
bandwidth.
descriptors. Note that care must be taken to minimize the number of pages marked as global, because the
retry protocol discussed in the previous section is used to enforce coherency and can require significant bus
bandwidth.
When the 750GX is not the address-bus master, GBL is an input. The 750GX snoops a transaction if TS and
GBL are asserted together in the same bus clock cycle (this is a qualified snooping condition). No snoop
update to the 750GX cache occurs if the snooped transaction is not marked global. This includes invalidation
cycles.
GBL are asserted together in the same bus clock cycle (this is a qualified snooping condition). No snoop
update to the 750GX cache occurs if the snooped transaction is not marked global. This includes invalidation
cycles.
When the 750GX detects a qualified snoop condition, the address associated with the TS is compared
against the data-cache tags. Snooping completes if no hit is detected. If, however, the address hits in the
cache, the 750GX reacts according to the MEI protocol shown in Figure 8-16, assuming the WIM bits are set
to write-back, caching-enabled, and coherency-enforced modes (WIM = 001).
against the data-cache tags. Snooping completes if no hit is detected. If, however, the address hits in the
cache, the 750GX reacts according to the MEI protocol shown in Figure 8-16, assuming the WIM bits are set
to write-back, caching-enabled, and coherency-enforced modes (WIM = 001).