u-blox AG NINAW10 Manual Do Utilizador
NINA-W10 series - Data Sheet
UBX-17065507 - R01
Interfaces
Page 13 of 44
2.7.5 I
2
C
Three I
2
C interfaces can be configured on any GPIO pins.
The NINA-W101/NINA-W102 modules can operate as both master and slave on the I
2
C bus using both standard
(100 kbps) and fast (400 kbps) transmission speeds. The interface uses the SCL signal to clock instructions and
data on the SDL signal.
data on the SDL signal.
2.7.6 SDIO
SDIO is multiplexed with the JTAG interface and the second SPI interface (SPI_H). It is possible to connect the
SDIO interfaces to other pin via the IO MUX but the speed is limited (see section 4.2.5). Only SDIO host is
supported (not SDIO slave).
SDIO interfaces to other pin via the IO MUX but the speed is limited (see section 4.2.5). Only SDIO host is
supported (not SDIO slave).
2.7.7 CAN
The NINA-W101/NINA-W102 modules support CAN2.0.
2.8 Debug interfaces
2.8.1 JTAG debug interfaces
The NINA-W101 and NINA-W102 modules support the JTAG debug interface (JTAG_TMS, JTAG_CLK,
JTAG_TDI and JTAG_TDO). The JTAG interface is multiplexed with the SDIO and the second SPI interface
(SPI_H).
JTAG_TDI and JTAG_TDO). The JTAG interface is multiplexed with the SDIO and the second SPI interface
(SPI_H).
2.9 Analog interfaces
2.9.1 Analog to digital converters
The NINA-W101 and NINA-W102 modules have four pins marked as Analog to Digital Converter (ADC) input
signals (ADC_2, ADC_3, ADC_4 and ADC_34), see chapter 3. These pins are primarily recommended for the
ADC application (to be compatible with future NINA modules). There are also 13 additional GPIO pins that can
be used for ADC application (see pins marked with an ADC-CH in the “ESP-32” column of Table 6. The analog
converters are 12-bit SAR ADCs. The NINA-W101 and NINAW102 modules can measure the voltages while
operating in the sleep mode, to enable low power consumption; the CPU can be woken up by a threshold
setting.
signals (ADC_2, ADC_3, ADC_4 and ADC_34), see chapter 3. These pins are primarily recommended for the
ADC application (to be compatible with future NINA modules). There are also 13 additional GPIO pins that can
be used for ADC application (see pins marked with an ADC-CH in the “ESP-32” column of Table 6. The analog
converters are 12-bit SAR ADCs. The NINA-W101 and NINAW102 modules can measure the voltages while
operating in the sleep mode, to enable low power consumption; the CPU can be woken up by a threshold
setting.
Analog pins cannot be re-routed to other pins via the IO MUX.
2.9.2 Digital to analog converters
Two 8-bit DAC channels ADC_16 and ADC_17 can be used to convert the two digital signals into two analog
voltage signal outputs. The design structure is composed of integrated resistor strings and a buffer. This dual
DAC has VCC as input voltage reference and can drive other circuits. The dual channels support independent
conversions.
voltage signal outputs. The design structure is composed of integrated resistor strings and a buffer. This dual
DAC has VCC as input voltage reference and can drive other circuits. The dual channels support independent
conversions.
Analog pins cannot be rerouted to other pins via the IO MUX.