Murata Electronics North America CCT24 Manual Do Utilizador
Page 52 of 90
CCT24
0x04
Even parity, 8 data bits, 1 stop bit
0x05
Even parity, 8 data bits, 2 stop bits
0x06
Odd parity, 8 data bits, 1 stop bit
0x07
Odd parity, 8 data bits, 2 stop bits
Note that 8-bit data with no parity is capable of carrying 7-bit data with parity for compatibility without loss
of generality for legacy applications that may require it.
of generality for legacy applications that may require it.
SerialControls - this parameter affects the way the radio responds to the various serial control lines.
Enabling or disabling response to some serial control signals can facilitate communicating with devices
that support only a reduced serial interface. The parameter is defined as a bitmask, with the following
options:
Enabling or disabling response to some serial control signals can facilitate communicating with devices
that support only a reduced serial interface. The parameter is defined as a bitmask, with the following
options:
bits 7..3
Reserved
bit 2
Base /DCD mode:
1 = The base will only assert /DCD when at least one remote is registered (default).
0 = The base always asserts /DCD, regardless of whether any remotes are attached.
0 = The base always asserts /DCD, regardless of whether any remotes are attached.
bit 1
/HOST_RTS enable:
1 = Radio will respond to changes on the /HOST_RTS control line (default).
0 = Radio ignores the /HOST_RTS pin and assumes flow control is always asserted.
0 = Radio ignores the /HOST_RTS pin and assumes flow control is always asserted.
bit 0
SLEEP/DTR enable.
1 = Radio will respond to changes on the SLEEP Pin (default)
0 = Radio ignores the SLEEP Pin and is always in the awake state.
0 = Radio ignores the SLEEP Pin and is always in the awake state.
SPI_Mode - this register enables and configures SPI port operation. When SPI functions are enabled, the
primary serial (UART) port operation is disabled in SPI Slave mode and restricted in SPI Master mode.
The diagnostic serial port continues to operate normally. Note that only protocol formatted messages can
be used when a CCT24 is configured for SPI operation. SPI_Mode has the following settings:
primary serial (UART) port operation is disabled in SPI Slave mode and restricted in SPI Master mode.
The diagnostic serial port continues to operate normally. Note that only protocol formatted messages can
be used when a CCT24 is configured for SPI operation. SPI_Mode has the following settings:
Setting
Mode
0x00
SPI disabled - serial UART mode (default)
0x01
SPI Slave mode
0x02
SPI Master mode
When a CCT24 is configured for SPI Slave mode operation, all messages are routed through the SPI port
in lieu of the primary serial (UART) port. The /HOST_CTS signal provides the same flow control function
for the MOSI input that it provides for the RADIO_RXD serial input. The Master (host) can clock transmit
messages into the CCT24 SPI Slave whenever /HOST_CTS is set to a logic low state. The Master can
also complete clocking a protocol formatted transmit message into the CCT24 if /HOST_CTS switches
high part way through the message, but must then stop inputting transmit messages until the CCT24
resets /HOST_CTS to a logic low state.
in lieu of the primary serial (UART) port. The /HOST_CTS signal provides the same flow control function
for the MOSI input that it provides for the RADIO_RXD serial input. The Master (host) can clock transmit
messages into the CCT24 SPI Slave whenever /HOST_CTS is set to a logic low state. The Master can
also complete clocking a protocol formatted transmit message into the CCT24 if /HOST_CTS switches
high part way through the message, but must then stop inputting transmit messages until the CCT24
resets /HOST_CTS to a logic low state.
In order for the Master to receive data from a CCT24 SPI Slave, it must clock bytes into the CCT24.
These bytes may be message bytes and/or 0x00 null bytes. The CCT24 will return null bytes on the MISO
output until the CCT24 receives a packet. The received message will then be clocked out. GPIO4 can be
alternately configured to provide an SPI RX data available flag, SPI_RX_AVL, to signal when the CCT24
slave is holding a received message(s). See Section 2.13 for additional information. In SPI Slave mode,
the maximum continuous SPI clock rate supported is 80.64 kb/s. The Master (host) clock rate should
closely match the CCT24 SPI clock rate setting for best data transfer efficiency. See the SPI_Divisor
description below.
These bytes may be message bytes and/or 0x00 null bytes. The CCT24 will return null bytes on the MISO
output until the CCT24 receives a packet. The received message will then be clocked out. GPIO4 can be
alternately configured to provide an SPI RX data available flag, SPI_RX_AVL, to signal when the CCT24
slave is holding a received message(s). See Section 2.13 for additional information. In SPI Slave mode,
the maximum continuous SPI clock rate supported is 80.64 kb/s. The Master (host) clock rate should
closely match the CCT24 SPI clock rate setting for best data transfer efficiency. See the SPI_Divisor
description below.
In SPI slave mode, de-asserting and then asserting the /SS line resets the CCT24 SPI port on a byte
boundary. The /SS line can be toggled this way between every byte to assure bit streams into and out of
the SPI port remain byte framed. Less frequent /SS line toggling is also acceptable in most applications. It
is recommended that /SS be toggled at the start and end of each transmit message, and after no more
than 256 null bytes when clocking to output a received message. The /SS line should also be toggled at
boundary. The /SS line can be toggled this way between every byte to assure bit streams into and out of
the SPI port remain byte framed. Less frequent /SS line toggling is also acceptable in most applications. It
is recommended that /SS be toggled at the start and end of each transmit message, and after no more
than 256 null bytes when clocking to output a received message. The /SS line should also be toggled at