Murata Electronics North America DNT900 Manual Do Utilizador
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©2008 by RF Monolithics, Inc.
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DNT900 - 11/05/08
Figure 5.6.3
Figure 5.6.3 shows the connectors to the left of the DNT900P mounting socket. Pressing switch SW2
switches GPIO0 from logic high to logic low. Pin strip J8 provides access to various DNT900 pins as
shown on the silkscreen. The wiper of pot R10 drives the input of ADC1. Clockwise rotation of the pot
wiper increases the voltage. Thermistor RT1 is part of a voltage divider that drives ADC0. LED D5 illumi-
nates when GPIO1 is set as a logic high output. LED D10 illuminates when GPIO3 is set as a logic high.
The DNT900P interface board includes a 5 V regulator to regulate the input from the 9 V wall transformer
power supply. Note: do not attempt to use the 9 V wall transformer power supply to power the DNT900P
directly. The maximum allowed voltage input to the DNT900P is 5.5 V.
switches GPIO0 from logic high to logic low. Pin strip J8 provides access to various DNT900 pins as
shown on the silkscreen. The wiper of pot R10 drives the input of ADC1. Clockwise rotation of the pot
wiper increases the voltage. Thermistor RT1 is part of a voltage divider that drives ADC0. LED D5 illumi-
nates when GPIO1 is set as a logic high output. LED D10 illuminates when GPIO3 is set as a logic high.
The DNT900P interface board includes a 5 V regulator to regulate the input from the 9 V wall transformer
power supply. Note: do not attempt to use the 9 V wall transformer power supply to power the DNT900P
directly. The maximum allowed voltage input to the DNT900P is 5.5 V.