Climax Technology Co Ltd ZBH-SA Manual Do Utilizador
The device contains flash memory for storage of program code.
The flash memory is programmable from the user software and through the debug interface.
The flash controller handles writing and erasing the embedded flash memory.
The flash controller allows page-wise erasure and 4-bytewise programming.
The I/O controller is responsible for all general-purpose I/O pins.
The CPU can configure whether peripheral modules control certain pins or whether they are under
software control, and if so, whether each pin is configured as an input or output and if a pullup or
pulldown resistor in the pad is connected. CPU interrupts can be enabled on each pin individually.
Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to
ensure flexibility in various applications.
A versatile five-channel DMA controller is available in the system, accesses memory using the
XDATA memory space, and thus has access to all physical memories.
Each channel (trigger, priority, transfer mode, addressing mode, source and destination pointers, and
transfer count) is configured with DMA descriptors anywhere in memory.
Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achieve
highly efficient operation by using the DMA controller for data transfers between SFR or XREG
addresses and flash/SRAM.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality.
It has a programmable prescaler, a 16-bit period value, and five individually programmable
counter/capture channels, each with a 16-bit compare value.
Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges
on input signals.
It can also be configured in IR Generation Mode where it counts Timer 3 periods and the output is
ANDed with the output of Timer 3 to generate modulated consumer IR signals with minimal CPU
interaction.
The MAC timer (Timer 2) is specially designed for supporting an IEEE 802.15.4 MAC or other
time-slotted protocol in software.
The timer has a configurable timer period and an 8-bit overflow counter that can be used to keep track
of the number of periods that have transpired.
A 16-bit capture register is also used to record the exact time at which a start-of-frame delimiter is
received/transmitted or the exact time at which transmission ends, as well as a 16-bit output compare
register that can produce various command strobes (start RX, start TX, etc.) at specific times to the
radio modules.
Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a
programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit
compare value.
Each of the counter channels can be used as a PWM output.
The sleep timer is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz RC oscillator