Glenayre Electronics Inc. GL-T8600-CN Manual Do Utilizador
Glenayre Document Number: 9110.00172
DSP Exciter
Issue 1, Rev. I: 01/15/97
THEORY OF OPERATION
Print Date: 02/19/97
Copyright © 1997 Glenayre
Page: 6-7
sec_
6
6.3.2.4
Read-Only Memory
A programmable and erasable read-only memory (PEROM) stores the modulator programs
for both DSPs. These programs are transferred to the SM when the exciter is booted up
(powered up), then the SM transfers the program to the DQM. The nonvolatile PEROM
retains its program for years. Its memory may be individually reprogrammed without
erasing the entire chip.
for both DSPs. These programs are transferred to the SM when the exciter is booted up
(powered up), then the SM transfers the program to the DQM. The nonvolatile PEROM
retains its program for years. Its memory may be individually reprogrammed without
erasing the entire chip.
6.4
IF Stage
Refer to
. The input to the IF
stage is the first IF signal, which is supplied by the DSP modulator circuit. The first IF
signal carries all the paging information on an intermediate carrier frequency. The IF stage
performs direct up-conversion of the first IF signal to create the second IF signal, which
carries the same paging information as the first IF signal, but on a higher carrier frequency.
The second IF signal is applied to the RF stage through connector pair J10/P10. To produce
the second IF signal, the IF stage contains mixer-1 and filter circuits. Supporting these
circuits are VCO-1 and synthesizer-1 circuits.
signal carries all the paging information on an intermediate carrier frequency. The IF stage
performs direct up-conversion of the first IF signal to create the second IF signal, which
carries the same paging information as the first IF signal, but on a higher carrier frequency.
The second IF signal is applied to the RF stage through connector pair J10/P10. To produce
the second IF signal, the IF stage contains mixer-1 and filter circuits. Supporting these
circuits are VCO-1 and synthesizer-1 circuits.
, show additional detail.
6.4.1
Mixer-1
Mixer-1 is the first heterodyne mixer. Inputs to mixer-1 are a modulated IF and a carrier.
The modulated IF input is the first IF signal. The carrier input is supplied by VCO-1. The
output from mixer-1 consists of two modulated carriers that are sums and difference
frequencies of the inputs. These two frequencies are applied to the filter circuit.
The modulated IF input is the first IF signal. The carrier input is supplied by VCO-1. The
output from mixer-1 consists of two modulated carriers that are sums and difference
frequencies of the inputs. These two frequencies are applied to the filter circuit.
6.4.2
Filter
The filter is centered at the second IF signal frequency with a 45-kHz bandwidth. The input
to the filter consists of two modulated carriers. These are sum and difference frequencies
supplied by mixer-1. The output from the filter is only the sum frequency. This modulated
output is the second IF signal.
to the filter consists of two modulated carriers. These are sum and difference frequencies
supplied by mixer-1. The output from the filter is only the sum frequency. This modulated
output is the second IF signal.
6.4.3
VCO-1
VCO-1 is the local oscillator for the IF stage. The input to VCO-1 is a dc control voltage.
This voltage controls VCO-1 carrier frequency and is supplied by synthesizer-1. The output
from VCO-1 is a sine-wave carrier. The output is applied to mixer-1.
This voltage controls VCO-1 carrier frequency and is supplied by synthesizer-1. The output
from VCO-1 is a sine-wave carrier. The output is applied to mixer-1.
6.4.4
Synthesizer-1
Synthesizer-1 controls VCO-1 carrier frequency by means of a phase-locked loop (PLL).
PLL inputs are a carrier and a phase reference. The reference input is a ten-MHz carrier
supplied by the ten-MHz reference circuit. The carrier input is from VCO-1. The PLL
output is a dc control voltage. This voltage, set to cause the VCO-1 carrier to lock phases
with the reference, is supplied to VCO-1.
PLL inputs are a carrier and a phase reference. The reference input is a ten-MHz carrier
supplied by the ten-MHz reference circuit. The carrier input is from VCO-1. The PLL
output is a dc control voltage. This voltage, set to cause the VCO-1 carrier to lock phases
with the reference, is supplied to VCO-1.