Intel P4500 CP80617004803AA Ficha De Dados
Códigos do produto
CP80617004803AA
Signal Description
72
Datasheet
SA_CKE[1:0]
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up
- Power-down SDRAM ranks
- Place all SDRAM ranks into and out of self-
refresh during STR
refresh during STR
O
DDR3
SA_CS#[1:0]
Chip Select: (1 per rank) Used to select
particular SDRAM components during the
active state. There is one Chip Select for
each SDRAM rank.
particular SDRAM components during the
active state. There is one Chip Select for
each SDRAM rank.
O
DDR3
SA_ODT[1:0]
On Die Termination: Active Termination
Control.
Control.
O
DDR3
Table 6-22.Memory Channel B (Sheet 1 of 2)
Signal Name
Description
Direction/
Buffer Type
SB_BS[2:0]
Bank Select: These signals define which
banks are selected within each SDRAM rank.
banks are selected within each SDRAM rank.
O
DDR3
SB_WE#
Write Enable Control Signal: Used with
SB_RAS# and SB_CAS# (along with
SB_CS#) to define the SDRAM Commands.
SB_RAS# and SB_CAS# (along with
SB_CS#) to define the SDRAM Commands.
O
DDR3
SB_RAS#
RAS Control Signal: Used with SB_CAS#
and SB_WE# (along with SB_CS#) to define
the SRAM Commands.
and SB_WE# (along with SB_CS#) to define
the SRAM Commands.
O
DDR3
SB_CAS#
CAS Control Signal: Used with SB_RAS#
and SB_WE# (along with SB_CS#) to define
the SRAM Commands.
and SB_WE# (along with SB_CS#) to define
the SRAM Commands.
O
DDR3
SB_DM[7:0]
Data Mask: These signals are used to mask
individual bytes of data in the case of a
partial write and to interrupt burst writes.
When activated during writes, the
corresponding data groups in the SDRAM are
masked. There is one SB_DM[7:0] for every
data byte lane.
individual bytes of data in the case of a
partial write and to interrupt burst writes.
When activated during writes, the
corresponding data groups in the SDRAM are
masked. There is one SB_DM[7:0] for every
data byte lane.
O
DDR3
SB_DQS[7:0]
Data Strobes: SB_DQS[7:0] and its
complement signal group make up a
differential strobe pair. The data is captured
at the crossing point of SB_DQS[7:0] and its
SB_DQS#[7:0] during read and write
transactions.
complement signal group make up a
differential strobe pair. The data is captured
at the crossing point of SB_DQS[7:0] and its
SB_DQS#[7:0] during read and write
transactions.
I/O
DDR3
SB_DQS#[7:0]
Data Strobe Complements: These are the
complementary strobe signals.
complementary strobe signals.
I/O
DDR3
SB_DQ[63:0]
Data Bus: Channel B data signal interface to
the SDRAM data bus.
the SDRAM data bus.
I/O
DDR3
Table 6-21.Memory Channel A (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type