Intel III Xeon 500 MHz 80525KX5001M Manual Do Utilizador
Códigos do produto
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
14
Datasheet
See
for the timing relationship between the system bus multiplier signals, RESET#, and
normal processor operation. Using CRESET# (CMOS Reset) and the timing shown in
circuit in
can be used to share these configuration signals. The component used as the
multiplexer must not have outputs that drive higher th an 2.5V in order to meet the processor’s
2.5 V tolerant buffer specifications. The multiplexer output current should be limited to 200mA
maximum, in case the V
2.5 V tolerant buffer specifications. The multiplexer output current should be limited to 200mA
maximum, in case the V
CCCORE
supply to the processor ever fails.
As shown in
, the pull-up resistors between the multiplexer and the processor (1 k
Ω
) force
a “safe” ratio into the processor in the event that the processor powers up before the multiplexer
and/or core logic. This prevents the processor from ever seeing a ratio higher than the final ratio.
and/or core logic. This prevents the processor from ever seeing a ratio higher than the final ratio.
If the multiplexer were powered by
CC2.5
, a pull-down resistor could be used on CRESET#
instead of the four pull-up resistors between the multiplexer and the Pentium
III
Xeon processors.
In this case, the multiplexer must be designed such that the compatibility inputs are truly ignored,
as their state is unknown.
as their state is unknown.
In any case, the compatibility inputs to the multiplexer must meet the input specifications of the
multiplexer. This may require a level translation before the multiplexer inputs unless the inputs and
the signals driving them are already compatible.
multiplexer. This may require a level translation before the multiplexer inputs unless the inputs and
the signals driving them are already compatible.
For FRC mode operation, these inputs to the processor must be synchronized using BCLK to meet
setup and hold times to the processors. This may require the use of high-speed programmable
logic.
setup and hold times to the processors. This may require the use of high-speed programmable
logic.
2/5
Not Supported
L
H
L
L
2/7
Not Supported
L
H
L
H
2/9
Not Supported
L
H
H
L
2/11
550 MH
L
H
H
H
1/6
Not Supported
H
L
L
L
1/7
Not Supported
H
L
L
H
1/8
Not Supported
H
L
H
L
Reserved
Not Supported
H
L
H
H
2/13
Not Supported
H
H
L
L
2/15
Not Supported
H
H
L
H
2/3
Not Supported
H
H
H
L
1/2
Reset Only
H
H
H
H
Table 1. Core Frequency to System Bus Multiplier Configuration
Multiplication of Processor
Core Frequency to System
Bus Frequency
Product Supported
on
LINT[1]
LINT[0]
A20M#
IGNNE#