Intel III Xeon 500 MHz 80525KX5001M Manual Do Utilizador
Códigos do produto
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
86
Datasheet
8.2
Integration Tool (Logic Analyzer) Considerations
Target platforms must be designed to allow for the mechanical keep-out zones. These keep-outs
allow a logic analyzer interface to be plugged in between the processor slots. Intel now uses only
third party solutions for logic analyzers. The companies that Intel has enabled at the time of
publication have been Hewlett-Packard* and Tektronix*. Please contact these vendors for the latest
keep-out zone information.
allow a logic analyzer interface to be plugged in between the processor slots. Intel now uses only
third party solutions for logic analyzers. The companies that Intel has enabled at the time of
publication have been Hewlett-Packard* and Tektronix*. Please contact these vendors for the latest
keep-out zone information.
9.0
Appendix
This appendix provides an alphabetical listing of all Pentium
III
Xeon processor signals and tables
that summarize the signals by direction: output, input, and I/O.
9.1
Alphabetical Signals Reference
This section provides an alphabetical listing of all Pentium
III
Xeon processor signals.
9.1.1
A[35:03]# (I/O)
The A[35:3]# (Address) signals define a 2
36
-byte physical memory address space. When ADS# is
active, these pins transmit the address of a transaction; when ADS# is inactive, these pins transmit
transaction type information. These signals must connect the appropriate pins of all agents on the
Pentium
transaction type information. These signals must connect the appropriate pins of all agents on the
Pentium
III
Xeon processor system bus. The A[35:24]# signals are parity-protected by the AP1#
parity signal, and the A[23:03]# signals are parity protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:03]# pins to
determine their power-on configuration. See the Pentium
determine their power-on configuration. See the Pentium
®
II Processor Developer’s Manual for
details.
9.1.2
A20M# (I)
If the A20M# (Address-20 Mask) input signal is asserted, the Pentium
III
Xeon processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode.
read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O
write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write
bus transaction.
write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write
bus transaction.
During active RESET#, each processor begins sampling the A20M#, IGNNE#, and LINT[1:0]
values to determine the ratio of core-clock frequency to bus-clock frequency. See
values to determine the ratio of core-clock frequency to bus-clock frequency. See
active-to-inactive transition of RESET#, each processor latches these signals and freezes the
frequency ratio internally. System logic must then release these signals for normal operation.
frequency ratio internally. System logic must then release these signals for normal operation.