Intel III Xeon 700 MHz 80526KY7002M Manual Do Utilizador
Códigos do produto
80526KY7002M
INTEGRATION TOOLS
79
Table 52. Debug Port Pinout Description and Requirements
1
Name Pin
Description
Specification
Requirement
Notes
BSEN#
14
Informs target system that
ITP is using boundary
scan.
Not required if boundary scan is not
used in target system.
PREQ0#
16
PREQ0# signal, driven by
ITP, makes requests to P0
to enter debug.
Add 150 to 330
Ω pull-up
resistor (to Vcc_
TAP
).
PRDY0#
18
PRDY0# signal, driven by
P0, informs ITP that P0 is
P0, informs ITP that P0 is
ready for debug.
Terminate
2
signal properly at
the debug port.
Debug port must be at the end
of the signal trace.
Connected to high-speed
comparator (biased at 2/3 of the
level found at the POWERON pin)
on the ITP buffer board. Additional
load does not change timing
calculations for the processor bus
agents if routed properly.
PREQ1#
20
PREQ1# signal from ITP to
P1.
Add 150 to 330
Ω pull-up
resistor (to Vcc_
TAP
)
PRDY1#
22
PRDY1# signal from P1 to
ITP.
Terminate
2
signal properly at
the debug port.
Debug port must be at the end
of the signal trace.
Connected to high-speed
comparator (biased at 2/3 of the
level found at the POWERON pin)
on the ITP buffer board. Additional
load does not change timing
calculations for the processor bus
agents.
PREQ2#
24
PREQ2# signal from ITP to
P2.
Add 150 to 330
Ω pull-up
resistor (to Vcc_
TAP
).
PRDY2#
26
PRDY2# signal from ITP to
P2.
Terminate
2
signal properly at
the debug port.
Debug port must be at the end
of the signal trace.
Connected to high-speed
comparator (biased at 2/3 of the
level found at the POWERON pin)
on the ITP buffer board. Additional
load does not change timing
calculations for the processor bus
agents if routed properly.
PREQ3#
28
PREQ3# signal from ITP to
P3.
Add 150 to 330
Ω pull-up
resistor (to Vcc_
TAP
).
PRDY3#
30
PRDY3# signal from ITP to
P3.
Terminate
2
signal properly at
the debug port.
Debug port must be at the end
of the signal trace.
Connected to high-speed
comparator (biased at 2/3 of the
level found at the POWERON pin)
on the ITP buffer board. Additional
load does not change timing
calculations for the processor bus
agents if routed properly.
BCLK
29
Bus clock from the MP
cluster.
Use a separate driver to drive
signal to the debug port.
A separate driver should be used to
avoid loading issues associated with
having the ITP either installed or not
installed.
GND
2, 4, 6,
13, 15,
17, 19,
21, 23,
13, 15,
17, 19,
21, 23,
25, 27
Signal ground.
Connect all pins to signal
ground.