Intel i7-3920XM Extreme AW8063801009607 Manual Do Utilizador
Códigos do produto
AW8063801009607
Processor Configuration Registers
166
Datasheet, Volume 2
2.10.4
PCISTS—PCI Status Register
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the Root port.
the "virtual" Host-PCI Express bridge embedded within the Root port.
B/D/F/Type:
0/6/0/PCI
Address Offset:
6–7h
Reset Value:
0010h
Access:
RW1C, RO, RO-V
Size:
16 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
15
RW1C
0b
Uncore
Detected Parity Error (DPE)
This bit is set by a Function whenever it receives a Poisoned TLP,
This bit is set by a Function whenever it receives a Poisoned TLP,
regardless of the state the Parity Error Response bit in the
Command register. On a Function with a Type 1 Configuration
header, the bit is set when the Poisoned TLP is received by its
Primary Side.
Reset Value of this bit is 0b.
This bit will be set only for completions of requests encountering
Reset Value of this bit is 0b.
This bit will be set only for completions of requests encountering
ECC error in DRAM.
Poisoned peer-2-peer posted forwarded will not set this bit. They
Poisoned peer-2-peer posted forwarded will not set this bit. They
are reported at the receiving port.
14
RW1C
0b
Uncore
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting
This bit is set when this Device sends an SERR due to detecting
an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable
bit in the Command register is '1'. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not affect
this field.
13
RO
0b
Uncore
Received Master Abort Status (RMAS):
This bit is set when a Requester receives a Completion with
This bit is set when a Requester receives a Completion with
Unsupported Request Completion Status. On a Function with a
Type 1 Configuration header, the bit is set when the Unsupported
Request is received by its Primary Side.
Not applicable. There is No UR on primary interface
Not applicable. There is No UR on primary interface
12
RO
0b
Uncore
Received Target Abort Status (RTAS)
This bit is set when a Requester receives a Completion with
This bit is set when a Requester receives a Completion with
Completer Abort Completion Status. On a Function with a Type 1
Configuration header, the bit is set when the Completer Abort is
received by its Primary Side.
Reset Value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a
Reset Value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a
Completer abort does not exist on primary side of this device.
11
RO
0b
Uncore
Signaled Target Abort Status (STAS):
This bit is set when a Function completes a Posted or Non-Posted
This bit is set when a Function completes a Posted or Non-Posted
Request as a Completer Abort error. This applies to a Function
with a Type 1 Configuration header when the Completer Abort
was generated by its Primary Side.
Reset Value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a
Reset Value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a
target abort does not exist on primary side of this device.
10:9
RO
00b
Uncore
DEVSELB Timing (DEVT)
This device is not the subtractively decoded device on bus 0. This
This device is not the subtractively decoded device on bus 0. This
bit field is therefore hardwired to 00 to indicate that the device
uses the fastest possible decode.
Does not apply to PCI Express and must be hardwired to 00b.
Does not apply to PCI Express and must be hardwired to 00b.