takeMS So dimm 512MB DDR2 DD512TEC905/A Manual Do Utilizador
Códigos do produto
DD512TEC905/A
DD512TEC905.fm Rev. B 07/2004
2
DD512TEC905
Pin Configurations Descriptions
SYMBOL
TYPE
FUNCTION
ODT0
Input
On-Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
CK0 ~ CK0#
CK1 ~ CK1#
CK1 ~ CK1#
Input
Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK, and negative edge of CK#. Output data (DQs and DQS) is
referenced to the crossings of CK and CK#.
the crossing of the positive edge of CK, and negative edge of CK#. Output data (DQs and DQS) is
referenced to the crossings of CK and CK#.
CKE0
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers, and
output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank).
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, and CKE) are dis-
abled during POWER-DOWN. Input buffers (Excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LCVMOS LOW level after VDD is applied.
output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank).
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, and CKE) are dis-
abled during POWER-DOWN. Input buffers (Excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LCVMOS LOW level after VDD is applied.
S0#
Input
Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
All commands are masked when S# is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the command code.
All commands are masked when S# is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the command code.
RAS#, CAS#, WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
BA0, BA1, BA2 (1GB) Input
Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRE-
CHARGE command is applied. BA0-BA2 define which mode register including MR, EMR, EMR(2),
and EMR(3) is loaded during the LOAD MODE command.
CHARGE command is applied. BA0-BA2 define which mode register including MR, EMR, EMR(2),
and EMR(3) is loaded during the LOAD MODE command.
A0 ~ A12 (256MB)
A0 ~ A13
(512MB, 1GB)
A0 ~ A13
(512MB, 1GB)
Input
Address Inputs: A0-A12 provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the mem-
ory array in the respective device bank. A10 sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0,
BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended
mode register) is loaded during the LOAD MODE REGISTER command.
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the mem-
ory array in the respective device bank. A10 sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0,
BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended
mode register) is loaded during the LOAD MODE REGISTER command.
DM0 ~ DM7
Input
Input Data Mask: DM is an input mask signal for write data. The data write masks associate with
one byte. In Write mode, DM operates as a byte mask allowing input data to be written if it is low but
blocks the write operation if it is high. In Read mode, DM lines have no effect.
one byte. In Write mode, DM operates as a byte mask allowing input data to be written if it is low but
blocks the write operation if it is high. In Read mode, DM lines have no effect.
DQ0 ~ DQ63
Input/
Output
Data I/Os: Bidirectional data bus.
V
DD
, V
DDSPD
, V
SS
Supply
Power supply for core, I/O, Serial Presence Detect, and ground for the module.
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
and out of the presence-detect portion of the module.
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to
and from the module.
and from the module.
SA0 ~ SA1
Input
Presence-Detect Address Inputs: These pins are used to configure the presence-detect device.
DU
-
Do not Use: These pins are not connected on this module but are assigned pins on other modules
in this product family.
in this product family.
NC
-
No Connect: These pins should be left uncovered.