HP A2Y15AV Manual Do Utilizador

Datasheet, Volume 2

49

Processor Configuration Registers 

This register combined with the Vendor Identification register uniquely identifies any 
PCI device. 

Since Device 0 does not physically reside on PCI_A many of the bits are not 
implemented.

15:4

RO-FW

015h

Uncore

Device Identification Number MSB (DID_MSB) 
This is the upper part of device identification assigned to the 

processor.

3:2

RO-V

00b

Uncore

Device Identification Number SKU (DID_SKU)
This is the middle part of device identification assigned to the 

processor.

1:0

RO-FW

00b

Uncore

Device Identification Number LSB (DID_LSB)
This is the lower part of device identification assigned to the 

processor.

15:10

RO

0h

9

RO

0b

Uncore

Fast Back-to-Back Enable (FB2B) 
This bit controls whether or not the master can do fast back-to-

back write. Since Device 0 is strictly a target this bit is not 

implemented and is hardwired to 0. Writes to this bit position 

have no effect.

8

RW

0b

Uncore

SERR Enable (SERRE) 
This bit is a global enable bit for Device 0 SERR messaging. The 

processor communicates the SERR condition by sending an SERR 

message over DMI to the PCH.
1 = The processor is enabled to generate SERR messages over 

DMI for specific Device 0 error conditions that are 

individually enabled in the ERRCMD and DMIUEMSK 

registers. The error status is reported in the ERRSTS, 

PCISTS, and DMIUEST registers.

0 = The SERR message is not generated by the Host for Device 

0. 

This bit only controls SERR messaging for Device 0. Other 

integrated devices have their own SERRE bits to control error 

reporting for error conditions occurring in each device. The 

control bits are used in a logical OR manner to enable the SERR 

DMI message mechanism.
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled