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Intel
G645T
Manual Do Utilizador
Intel G645T CM8062301263701 Manual Do Utilizador
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CM8062301263701
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Datasheet, Volume 2
5
2.6.30
MC—Message Control Register ............................................................ 108
2.6.31
MA—Message Address Register ........................................................... 109
2.6.32
MD—Message Data Register ............................................................... 109
2.6.33
PEG_CAPL—PCI Express-G Capability List Register................................. 109
2.6.34
PEG_CAP—PCI Express-G Capabilities Register ...................................... 110
2.6.35
DCAP—Device Capabilities Register...................................................... 110
2.6.36
DCTL—Device Control Register............................................................ 111
2.6.37
DSTS—Device Status Register............................................................. 112
2.6.38
LCTL—Link Control Register ................................................................ 113
2.6.39
LSTS—Link Status Register................................................................. 115
2.6.40
SLOTCAP—Slot Capabilities Register .................................................... 116
2.6.41
SLOTCTL—Slot Control Register .......................................................... 118
2.6.42
SLOTSTS—Slot Status Register ........................................................... 120
2.6.43
RCTL—Root Control Register ............................................................... 122
2.6.44
LCTL2—Link Control 2 Register ........................................................... 123
2.7
PCI Device 1, Function 0–2 Extended Configuration Registers................................ 125
2.7.1
PVCCAP1—Port VC Capability Register 1 ............................................... 125
2.7.2
PVCCAP2—Port VC Capability Register 2 ............................................... 126
2.7.3
PVCCTL—Port VC Control Register ....................................................... 126
2.7.4
VC0RCAP—VC0 Resource Capability Register......................................... 127
2.7.5
VC0RCTL—VC0 Resource Control Register............................................. 128
2.7.6
VC0RSTS—VC0 Resource Status Register ............................................. 129
2.7.7
PEG_TC—PCI Express Completion Time-out Register .............................. 129
2.8
PCI Device 2 Configuration Registers ................................................................. 130
2.8.1
VID2—Vendor Identification Register ................................................... 131
2.8.2
DID2—Device Identification Register.................................................... 131
2.8.3
PCICMD2—PCI Command Register....................................................... 132
2.8.4
PCISTS2—PCI Status Register............................................................. 133
2.8.5
RID2—Revision Identification Register.................................................. 134
2.8.6
CC—Class Code Register .................................................................... 134
2.8.7
CLS—Cache Line Size Register ............................................................ 135
2.8.8
MTXT2—Master Latency Timer Register ................................................ 135
2.8.9
HDR2—Header Type Register .............................................................. 135
2.8.10
GTTMMADR—Graphics Translation Table, Memory
Mapped Range Address Register.......................................................... 136
2.8.11
GMADR—Graphics Memory Range Address Register ............................... 137
2.8.12
IOBAR—I/O Base Address Register ...................................................... 138
2.8.13
SVID2—Subsystem Vendor Identification Register ................................. 138
2.8.14
SID2—Subsystem Identification Register .............................................. 139
2.8.15
ROMADR—Video BIOS ROM Base Address Register ................................ 139
2.8.16
INTRPIN—Interrupt Pin Register .......................................................... 139
2.8.17
MINGNT—Minimum Grant Register ...................................................... 140
2.8.18
MAXLAT—Maximum Latency Register ................................................... 140
2.8.19
MSAC—Multi Size Aperture Control Register .......................................... 141
2.9
Device 2 I/O Registers ..................................................................................... 142
2.9.1
INDEX—MMIO Address Register .......................................................... 142
2.9.2
DATA—MMIO Data Register ................................................................ 142
2.10 PCI Device 6 Configuration Registers ................................................................. 143
2.10.1
VID6—Vendor Identification Register ................................................... 144
2.10.2
DID6—Device Identification Register.................................................... 145
2.10.3
PCICMD6—PCI Command Register....................................................... 145
2.10.4
PCISTS6—PCI Status Register............................................................. 147
2.10.5
RID6—Revision Identification Register.................................................. 149
2.10.6
CC6—Class Code Register................................................................... 149
2.10.7
CL6—Cache Line Size Register ............................................................ 150
2.10.8
HDR6—Header Type Register .............................................................. 150
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