Intel G1610T CM8063701445100 Manual Do Utilizador

Datasheet

1095

PCU_SMB_ALERT# is multiplexed with GPIO_S0_SC[53]. When enabled and the signal 
is asserted, the processor can generate an interrupt or an SMI#.

Using this signal as a wake event from S3–S5 is not supported.

If the SMB_Mem_AUXC.AAC is set, the processor automatically calculates and drives 
CRC at the end of the transmitted packet for write cycles, and will check the CRC for 
read cycles. It will not transmit the contents of the Packet Error Check Data Register 
(SMB_Mem_PEC) PEC register for CRC. The SMB_Mem_HCTL.PECEN bit must not be 
set if this bit is set, or unspecified behavior will result.

If the read cycle results in a CRC error, the SMB_Mem_HSTS.DEVERR bit and the 
SMB_Mem_AUXS.CRCE bit will be set.

PCU_SMB_ALERT# 

asserted low (always 

reported in 

SMB_Mem_

HSTS.SMBALERT)

X

1

0

Slave  SMI# 

generated

(SMBUS_SMI_STS

)

1

0

0

Interrupt 

generated

Any combination of 

SMB_Mem_HSTS.

FAILED, 

SMB_Mem_HSTS.

BERR, SMB_Mem_HSTS.

DEVERR, 

SMB_Mem_HSTS.

INTR asserted

0

X

None

1

0

Interrupt generated

1

1

Host  SMI#  generated

0

X

0

None

1

0

X

Interrupt generated

1

1

X

Slave SMI# generated 

(SMBUS_SMI_STS)