Intel 1020M AW8063801443700 Manual Do Utilizador
Códigos do produto
AW8063801443700
Datasheet, Volume 1
13
Introduction
1.1
Processor Feature Details
• Four or two execution cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction / data second-level cache (L2) for each core
• Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction / data second-level cache (L2) for each core
• Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores
1.1.1
Supported Technologies
• Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O (Intel
®
VT-d)
• Intel
®
Virtualization Technology (Intel
®
VT) for IA-32, Intel
®
64 and Intel
®
Architecture (Intel
®
VT-x)
Intel
®
Active Management Technology (Intel
®
AMT) 8.0
• Intel
®
Trusted Execution Technology (Intel
®
TXT)
• Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
• Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
• Intel
®
Hyper-Threading Technology (Intel
®
HT Technology)
• Intel
®
64 Architecture
• Execute Disable Bit
• Intel
• Intel
®
Turbo Boost Technology
• Intel
®
Advanced Vector Extensions (Intel
®
AVX)
• Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI)
• PCLMULQDQ Instruction
• RDRAND instruction for random number generation
• SMEP – Supervisor Mode Execution Protection
• PAIR – Power Aware Interrupt Routing
• RDRAND instruction for random number generation
• SMEP – Supervisor Mode Execution Protection
• PAIR – Power Aware Interrupt Routing
1.2
Interfaces
1.2.1
System Memory Support
• Two channels of DDR3 / DDR3L / DDR3L-RS memory with Unbuffered Small Outline
Dual In-Line Memory Modules (SO-DIMM) with a maximum of two DIMMs per
channel
Note: 2 DIMMs per channel supported only in Quad-Core rPGA package only
channel
Note: 2 DIMMs per channel supported only in Quad-Core rPGA package only
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• System Memory Interface I/O Voltage of 1.35 V and 1.5
• Data burst length of eight for all memory organization modes
• System Memory Interface I/O Voltage of 1.35 V and 1.5
V
• DDR3, DDR3L, and DDR3L-RS DIMMs / DRAMs running at 1.5 V
• DDR3L and DDR3L-RS DIMMs / DRAMS running at 1.35 V
• Support memory configurations that mix DDR3 DIMMs / DRAMs with DDR3L /
• DDR3L and DDR3L-RS DIMMs / DRAMS running at 1.35 V
• Support memory configurations that mix DDR3 DIMMs / DRAMs with DDR3L /
DDR3L-RS DIMMs / DRAMs running at 1.5 V
• 64-bit wide channels
• Non-ECC, Unbuffered DDR3 / DDR3L / DDR3L-RS SO-DIMMs only
• Theoretical maximum memory bandwidth of:
• Non-ECC, Unbuffered DDR3 / DDR3L / DDR3L-RS SO-DIMMs only
• Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s