Elpida 1GB DDR3 1600MHz EDJ1116EJBG Manual Do Utilizador

Preliminary Data Sheet E1949E11 (Ver. 1.1)

12

Notes: 1.

Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0].

2.

MR: Mode Register
Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1];
RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0].

3.

Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit.

4.

Auto self-refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature.

5.

Self-refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range.

6.

Read burst type: nibble sequential, set MR0 bit A3 = 0 

Operating burst write current

IDD4W

CKE: H; External clock: on; tCK, CL: see 

Table 5

; AL: 0; /CS: H between WR; 

command, address, bank address inputs: partially toggling according to 

; 

data I/O: seamless write data burst with different data between one burst and the next 
one according to IDD4W Measurement-Loop Pattern table; DM: stable at 0; bank 
activity: all banks open, 
WR commands cycling through banks: 0,0,1,1,2,2,.. (see 

); Output buffer 

and RTT: enabled in MR*

; ODT signal: stable 

at H; pattern details: see 

Burst refresh current

IDD5B

CKE: H; External clock: on; tCK, CL, nRFC: see 

Table 5

; AL: 0; /CS: H 

between REF; 
Command, address, bank address Inputs: partially toggling according to 

data I/O: MID-LEVEL; DM: stable at 0; 
bank activity: REF command every nRFC (

); output buffer and RTT: enabled 

in MR*

; ODT signal: stable at 0; pattern

Self-refresh current: normal 
temperature range

IDD6

TC: 0 to 85

°C; ASR: disabled*

; SRT:

Normal*

; CKE: L; External clock: off; CK and /CK: L; CL: see 

Table 5

; BL: 8*

AL: 0; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable 
at 0; bank activity: Self-refresh operation; output buffer and RTT: enabled in MR*

; 

ODT signal: MID-LEVEL

Self-refresh current: extended 
temperature range

IDD6ET

TC: 0 to 95

°C; ASR: Disabled*

; CKE: L; External clock: off; CK 

and /CK: L; CL: 

Table 5

; AL: 0; /CS, command, address, bank address, data 

I/O: MID-LEVEL;
DM: stable at 0; bank activity: Extended temperature self-refresh operation; output 
buffer and RTT: enabled in MR*

; ODT signal: MID-LEVEL

Auto self-refresh current 
(Optional)

IDD6TC

TC: 0 to 95

°C; ASR: Enabled*

; SRT: Normal*

; CKE: L; External clock: off; 

CK and /CK: L; CL: 

Table 5

; AL: 0; /CS, command, address, bank address, 

data I/O: MID-LEVEL; DM: stable at 0; bank activity: Auto self-refresh operation; 
output buffer and RTT: enabled in MR*

; ODT signal: MID-LEVEL

Operating bank interleave 
read current

IDD7

CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see 

Table 5

; 

; AL: CL-1; /CS: H between ACT and RDA; Command, address, bank 

address Inputs: partially toggling according to 

; data I/O: read data bursts 

with different data between one burst and the next one according to 

stable at 0; bank activity: two times interleaved cycling through banks (0, 1, …7) with 
different addressing, see 

; output buffer and RTT: enabled in MR*

signal: stable at 0; pattern details: see 

RESET low current

IDD8

/RESET: low; External clock: off; CK and /CK: low; CKE: FLOATING; /CS, command, 
address, bank address, Data IO: FLOATING; ODT signal: FLOATING
RESET low current reading is valid once power is stable and /RESET has been low 
for at least 1ms.