Elpida 1GB DDR3 1600MHz EDJ1116EJBG Manual Do Utilizador

Preliminary Data Sheet E1949E11 (Ver. 1.1)

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Notes: 1.

The CL setting and CWL setting result in tCK(avg)min and tCK(avg)max requirements. When making a selection of 
tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.

2.

tCK(avg)min limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all 
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard 
tCK(avg) value (3.0, 2.5, 1.875, 1.5, or 1.25ns) when calculating CL(nCK) = tAA(ns) / tCK(avg)(ns), rounding up to the 
next ‘Supported CL’.

3.

tCK(avg)max limits: Calculate tCK(avg) + tAA(max)/CL selected and round the resulting tCK(avg) down to the next valid 
speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK(avg)max corresponding to CL selected.

4.

Reserved’ settings are not allowed. User must program a different value.

5.

Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1066 
Speed Bins which are not subject to production tests but verified by design/characterization.

6.

Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1333 
Speed Bins which is not subject to production tests but verified by design/characterization.

7.

Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1600 
Speed Bins which is not subject to production tests but verified by design/characterization.

8.

Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1866 
Speed Bins which is not subject to production tests but verified by design/characterization.

9.

tREFI depends on operating case temperature (TC).

10. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min) must be 13.125 ns or lower. SPD 

settings must be programmed to match.

11. DDR3-800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.