Elpida 1GB DDR3 1600MHz EDJ1116EJBG Manual Do Utilizador

Preliminary Data Sheet E1949E11 (Ver. 1.1)

7

Notes: 1.

Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very 
long period of time (e.g. 1 sec).

2.

If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.

3.

Under these supply voltages, the device operates to this DDR3L specifcation.

4.

Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while

5.

VDD and VDDQ are changed for DDR3 operation shown as following timing wave form.

Notes: 1.

If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.

2.

Under 1.5V operation, this DDR3L device operates to the DDR3 specifcations under the same speedtimings as defined 
for this device.

3.

Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ 
are changed for DDR3L operation shown as below.

°C to +85°C), DDR3L Operation

Supply voltage

VDD

1.283

1.35

1.45

V

1, 2, 3, 4

Supply voltage for DQ

VDDQ

1.283

1.35

1.45

V

1, 2, 3, 4

°C to +85°C), DDR3 Operation

Supply voltage

VDD

1.425

1.5

1.575

V

1, 2, 3

Supply voltage for DQ

VDDQ

1.425

1.5

1.575

V

1, 2, 3

T(min) = 10ns

T(min) = 200

µs

T(min) = 10ns

T = 500

µs

tIS

Note: 1.  From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands.

: VIH or VIL

CK, /CK

VDD, VDDQ (DDR3)

VDD, VDDQ (DDR3L)

/RESET

CKE

Command

BA

ODT

RTT

tXPR

tMRD

tMRD

tMRD

tMOD

tCKSRX

tIS

tIS

tIS

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

Tj

Tk

T(min) = 10ns

tDLLK

tZQinit

*1

*1

Valid

Valid

Valid

Valid

MRS

Static low in case RTT_Nore is enabled at time Tg, otherwise static high or low

MRS

MRS

MRS

ZQCL

MR2

MR3

MR1

MR0