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Intel
G1620T
Manual Do Utilizador
Intel G1620T CM8063701448300 Manual Do Utilizador
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CM8063701448300
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Datasheet
Table 166
Summary of PCU SMBus I/O Registers—SMB_Config_IOBAR..................... 1125
Table 167
iLB Signals......................................................................................... 1139
Table 168
NMI Sources ...................................................................................... 1140
Table 169
Summary of PCU iLB Interrupt Decode and Route Memory Mapped I/O
Registers—ILB_BASE_ADDRESS ........................................................... 1141
Table 170
LPC Signals........................................................................................ 1181
Table 171
SERIRQ, Stop Frame Width to Operation Mode Mapping ........................... 1184
Table 172
SERIRQ Interrupt Mapping ................................................................... 1185
Table 173
Summary of PCU iLB Low Pin Count (LPC) Bridge PCI Configuration
Registers—0/31/0............................................................................... 1189
Table 174
Summary of PCU iLB LPC BIOS Control Memory Mapped I/O Registers—
RCRB_BASE_ADDRESS........................................................................ 1209
Table 175
RTC Signals ....................................................................................... 1210
Table 176
Register Bits Reset by ILB_RTC_RST# Assertion ..................................... 1213
Table 177
I/O Registers Alias Locations ................................................................ 1214
Table 178
RTC Indexed Registers ........................................................................ 1214
Table 179
Summary of PCU iLB Real Time Clock (RTC) I/O Registers........................ 1216
Table 180
8254 Signals ...................................................................................... 1218
Table 181
Counter Operating Modes .................................................................... 1220
Table 182
Register Aliases .................................................................................. 1222
Table 183
Summary of PCU iLB 8254 Timers I/O Registers...................................... 1223
Table 184
8254 Interrupt Mapping....................................................................... 1231
Table 185
Summary of PCU iLB High Performance Event Timer (HPET) Memory
Mapped I/O Registers.......................................................................... 1232
Table 186
GPIO Signals...................................................................................... 1241
Table 187
Summary of PCU iLB I/O APIC Memory Mapped I/O Registers ................... 1251
Table 188
Interrupt Controller Connections ........................................................... 1253
Table 189
Interrupt Status Registers.................................................................... 1254
Table 190
Content of Interrupt Vector Byte........................................................... 1255
Table 191
I/O Registers Alias Locations ................................................................ 1260
Table 192
Summary of PCU iLB 8259 Interrupt Controller (PIC) I/O Registers............ 1262
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