Intel G1620T CM8063701448300 Manual Do Utilizador

970

Datasheet

23:16

0b

RO

Power Management Controller Revision ID (PMC_REVID) (pmc_revid): This 

field communicates the implementation revision of the power management functionality.

15

0b

RW

PMC Watchdog Timer Status (PMC_WDT_STS) (pmc_wdt_sts): This bit will be 

set to '1' when the PMC Watch Dog Timer triggers a reset. It will be cleared by a write of 

'1' by software.

14:12

0b

RO

reserved: Reserved.

11

0b

RO

Code Copied Over Status (CODE_COPIED_STS) (code_copied_sts): The 

processor sets this bit when PMC code is successfully authenticated and loaded from the 

flash

10

0b

RO

reserved (reserved1): Reserved.

9

0b

RO

Code Load Timeout Status (CODE_LOAD_TO) (code_load_to): The processor sets 

this bit if the loading function fails to complete within a reasonable time limit. This bit 

remains valid after a PMC Code load is attempted until the next global reset

8

0b

RO

PMC Operational Status (PMC_OP_STS) (pmc_op_sts): The processor sets this bit 

when the PMC becomes operational after completing the Code Load. BIOS must wait for 

this bit to be set before performing resets or sleep events. This bit remains valid after a 

PMC Code load until the next global reset

7

0b

RW

SEC Watch Dog Timer Status (SEC_GBLRST_STS) (sec_gblrst_sts): This bit will 

be set to '1' when the SEC FW triggers a reset. It will be cleared by a write of '1' by 

software.

6

0b

RW

SEC Watch Dog Timer Status (SEC_WDT_STS) (sec_wdt_sts): This bit will be set 

to '1' when the SEC Watch Dog Timer triggers a reset. It will be cleared by a write of '1' 

by software.

5

0b

RW

This bit gets set when integrated LAN Signals a Power Management Event AND the 

system is in S5. BIOS can read this status bit to determine this wake source. Software 

clears this bit by writing a 1 to it.

4

0b

RW

PMC_HOST_WAKE_STS (PMC_HOST_WAKE_STS) (pmc_host_wake_sts): The 

processor Power Management Controller sets this bit if it wakes the host for reasons 

other than typical host-visible wake events. This status bit provides information to BIOS 

that the PMC caused the wake.

3:0

0b

RO

reserved2: Reserved.