Intel E7-8891 v2 CM8063601377422 Manual Do Utilizador

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

135

Datasheet Volume Two: Functional Description, February 2014

bit[10:0]: Max number of transactions (ACT, READ, WRITE) to be allowed during the 1 
usec throttling timeframe per power throttling.

24:24

RW1C

0x0

Event Asserted on TEMPOEMHI Going High (ev_asrt_tempoemhi):

Event Asserted on TEMPOEMHI Going High
It is assumed that each of the event assertion is going to trigger Configurable 

interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 

of CHN_TEMP_CFG

23:8

RV

-

Reserved.

7:0

RW_LV

0x55

DIMM_TEMP (dimm_temp):

Current DIMM Temperature for thermal throttlingLock by 

CLTT_DEBUG_DISABLE_LOCK
When the CLTT_DEBUG_DISABLE_LOCK is cleared (unlocked), debug software 

can write to this byte to test various temperature scenarios.
When the CLTT_DEBUG_DISABLE_LOCK is set, this field becomes read-only, 

i.e. configuration write to this byte is aborted. This byte is updated from 

internal logic from a 2:1 Mux which can be selected from either CLTT 

temperature or from the corresponding   temperature registers output 

(PCODE_TEMP_OUTPUT) updated from PCU microcode. The mux select is 

controlled by CLTT_OR_PCODE_TEMP_MUX_SEL defined in CHN_TEMP_CFG 

register.
Valid range from 0 to 127 (i.e. 0C to +127C). Any negative value read 

from TSOD is forced to 0. TSOD decimal point value is also truncated to 

integer value.

The default value is changed to 85C to avoid missing refresh during S3 resume 

or during warm-reset flow after the DIMM is exiting self-refresh. The correct 

temperature may not be fetched from TSOD yet but the DIMM temperature 

may be still high and need to be refreshed at 2x rate.

15:15

RW

0x1

THRT_PWR_EN (thrt_pwr_en):

bit[15]: set to one to enable the power throttling for the DIMM.

14:12

RV

-

Reserved.

11:0

RW

0xfff

Power Throttling Control (thrt_pwr):

bit[11:0]: Max number of transactions (ACT, READ, WRITE) to be allowed 

(per DIMM) during the 1 micro-sec throttling timeframe per power 

throttling.

PCU microcode can update this register dynamically.