Intel E7-8891 v2 CM8063601377422 Manual Do Utilizador

180

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

24:24

RO_FW

0x0

XSAVE_DIS:

Disable the following instructions: XSAVE, XSAVEOPT, XRSTOR, XSETBV and 

XGETBV. 

23:23

RO_FW

0x0

AES_DIS:

Disable AES

22:22

RO_FW

0x0

TSC_DEADLINE_DIS:

APIC timer last tick relative mode:
 Disable support for TSC Deadline

21:21

RO_FW

0x0

LT_SMM_INHIBIT:

Intel TXT for handling of SMI inhibit with opt-out SMM

20:20

RO_FW

0x0

LT_SX_EN:

Intel

®

TXT and FIT-boot Enable

19:19

RO_FW

0x0

LT_PRODUCTION:

Intel

®

TXT Production 

 1. Intel

®

TXT-enable == SMX enable

 2. LTSX enable == FIT boot enable
 3. Intel

®

TXT production

 
 Legal combination (assume 0/1 == disable/enable)
 SMX (LT) enable FIT boot enable Intel TXT Production Remark 
 

0 

0 

0 

Intel TXT is disabled 

 

1 

1 

1 

Intel TXT/LTSX enabled (production)

 

1 

1 

0 

Intel TXT/LTSX enabled (non production)

 

1 

0 

1 

Intel TXT enabled (no LTSX)-single package 

(production)
 

1 

0 

0 

Intel TXT enabled (no LTSX)-single package (non 

production)

18:18

RO_FW

0x0

SMX_DIS:

Disable SMX

17:17

RO_FW

0x0

VMX_DIS:

Disable VMX

16:16

RO_FW

0x0

CORECONF_RES12:

Core configuration reserved bit 12

15:15

RO_FW

0x0

VT_X3_EN:

Enable VT-x3

14:14

RO_FW

0x0

VT_REAL_MODE:

VT Real mode

13:13

RO_FW

0x0

VT_CPAUSE_EN:

Enable CPAUSE - conditional PAUSE loop exiting; New VMX control to allow exit 

on PAUSE loop that are longer than a specified Window