Intel E7-8891 v2 CM8063601377422 Manual Do Utilizador

336

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Attention Status.

The Intel® Quick Data version register field indicates the version of the Intel® Quick 
Data specification that the IIO implements. The most significant 4-bits (range 7:4) are 
the major version number and the least significant 4-bits (range 3:0) are the minor 
version number. The IIO implementation for this Intel® Quick Data version is 3.2 
encoded as 0b0011 0010.

1:1

RO

0x0

intp_sts:

Interrupt Status. This bit is set whenever the bit in the Attention Status 

register is set. This bit is not used by software in MSI-X mode and is a don’t 

care.

0:0

RW

0x0

mstr_intp_en:

Master Interrupt Enable. Setting this bit enables the generation of an 

interrupt in legacy interrupt mode. This bit is automatically reset each time 

this register is read. When this bit is clear ed, the IIO will not generate a 

legacy interrupt under otherwise valid conditions. This bit is not used when 

DMA is in MSI-X mode.

31:1

RV

-

Reserved. 

0:0

RO_V

0x0

chanattn:

Channel Attention. Represents the interrupt status of the channel. This bit 

clears when read. Writes have no impact on this bit.

7:4

RO

0x3

mjrver:

Major Version. Specifies Major version of the Intel® Quick Data 

implementation. Current value is 2h

3:0

RO

0x2

mnrver:

Minor Version. Specifies Minor version of the Intel® Quick Data 

implementation. Current value is 0h